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[NFC][ARM] Fix update_llc_test_checks for thumbv7-apple-darwin, autogenerate thumb2-ifcvt1.ll
This commit is contained in:
Roman Lebedev
parent
285eb4c722
commit
3b18af59bd
@ -1,15 +1,19 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it -enable-tail-merge=0 | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefixes=ALL,V01
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s --check-prefixes=ALL,V01
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; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it | FileCheck %s --check-prefixes=ALL,V23,V2
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; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it -enable-tail-merge=0 | FileCheck %s --check-prefixes=ALL,V23,V3
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; CHECK-LABEL: t1:
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; CHECK: ittee ne
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; CHECK: cmpne
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; CHECK: addne
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; CHECK: addeq
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; CHECK: addeq
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; CHECK: bx lr
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; ALL-LABEL: t1:
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; ALL: @ %bb.0:
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; ALL-NEXT: cmp r2, #7
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; ALL-NEXT: ittee ne
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; ALL-NEXT: cmpne r2, #1
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; ALL-NEXT: addne r0, r1
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; ALL-NEXT: addeq r0, r1
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; ALL-NEXT: addeq r0, #1
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; ALL-NEXT: bx lr
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switch i32 %c, label %cond_next [
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i32 1, label %cond_true
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i32 7, label %cond_true
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@ -26,11 +30,54 @@ cond_next:
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}
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define i32 @t2(i32 %a, i32 %b) nounwind {
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; V01-LABEL: t2:
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; V01: @ %bb.0: @ %entry
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; V01-NEXT: cmp r0, r1
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; V01-NEXT: it eq
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; V01-NEXT: bxeq lr
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; V01-NEXT: LBB1_1: @ %bb
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; V01-NEXT: @ =>This Inner Loop Header: Depth=1
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; V01-NEXT: cmp r0, r1
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; V01-NEXT: ite gt
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; V01-NEXT: subgt r0, r0, r1
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; V01-NEXT: suble r1, r1, r0
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; V01-NEXT: cmp r1, r0
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; V01-NEXT: bne LBB1_1
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; V01-NEXT: @ %bb.2: @ %bb17
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; V01-NEXT: bx lr
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;
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; V2-LABEL: t2:
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; V2: @ %bb.0: @ %entry
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; V2-NEXT: cmp r0, r1
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; V2-NEXT: it eq
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; V2-NEXT: bxeq lr
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; V2-NEXT: .LBB1_1: @ %bb
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; V2-NEXT: @ =>This Inner Loop Header: Depth=1
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; V2-NEXT: cmp r0, r1
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; V2-NEXT: ite gt
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; V2-NEXT: subgt r0, r0, r1
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; V2-NEXT: suble r1, r1, r0
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; V2-NEXT: cmp r1, r0
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; V2-NEXT: bne .LBB1_1
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; V2-NEXT: @ %bb.2: @ %bb17
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; V2-NEXT: bx lr
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;
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; V3-LABEL: t2:
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; V3: @ %bb.0: @ %entry
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; V3-NEXT: cmp r0, r1
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; V3-NEXT: it eq
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; V3-NEXT: bxeq lr
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; V3-NEXT: .LBB1_1: @ %bb
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; V3-NEXT: @ =>This Inner Loop Header: Depth=1
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; V3-NEXT: cmp r0, r1
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; V3-NEXT: ite le
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; V3-NEXT: suble r1, r1, r0
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; V3-NEXT: subgt r0, r0, r1
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; V3-NEXT: cmp r1, r0
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; V3-NEXT: bne .LBB1_1
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; V3-NEXT: @ %bb.2: @ %bb17
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; V3-NEXT: bx lr
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entry:
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; CHECK-LABEL: t2:
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; CHECK: ite {{gt|le}}
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; CHECK-DAG: suble
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; CHECK-DAG: subgt
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%tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
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br i1 %tmp1434, label %bb17, label %bb.outer
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@ -64,11 +111,75 @@ bb17: ; preds = %cond_false, %cond_true, %entry
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}
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define i32 @t2_nomerge(i32 %a, i32 %b) nounwind {
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; V01-LABEL: t2_nomerge:
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; V01: @ %bb.0: @ %entry
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; V01-NEXT: cmp r0, r1
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; V01-NEXT: it eq
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; V01-NEXT: bxeq lr
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; V01-NEXT: LBB2_1: @ %bb
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; V01-NEXT: @ =>This Inner Loop Header: Depth=1
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; V01-NEXT: cmp r0, r1
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; V01-NEXT: ble LBB2_3
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; V01-NEXT: @ %bb.2: @ %cond_true
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; V01-NEXT: @ in Loop: Header=BB2_1 Depth=1
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; V01-NEXT: subs r0, r0, r1
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; V01-NEXT: cmp r1, r0
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; V01-NEXT: bne LBB2_1
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; V01-NEXT: b LBB2_4
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; V01-NEXT: LBB2_3: @ %cond_false
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; V01-NEXT: @ in Loop: Header=BB2_1 Depth=1
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; V01-NEXT: subs r1, r1, r0
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; V01-NEXT: cmp r0, #0
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; V01-NEXT: bne LBB2_1
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; V01-NEXT: LBB2_4: @ %bb17
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; V01-NEXT: bx lr
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;
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; V2-LABEL: t2_nomerge:
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; V2: @ %bb.0: @ %entry
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; V2-NEXT: cmp r0, r1
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; V2-NEXT: it eq
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; V2-NEXT: bxeq lr
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; V2-NEXT: .LBB2_1: @ %bb
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; V2-NEXT: @ =>This Inner Loop Header: Depth=1
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; V2-NEXT: cmp r0, r1
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; V2-NEXT: ble .LBB2_3
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; V2-NEXT: @ %bb.2: @ %cond_true
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; V2-NEXT: @ in Loop: Header=BB2_1 Depth=1
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; V2-NEXT: subs r0, r0, r1
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; V2-NEXT: cmp r1, r0
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; V2-NEXT: bne .LBB2_1
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; V2-NEXT: b .LBB2_4
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; V2-NEXT: .LBB2_3: @ %cond_false
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; V2-NEXT: @ in Loop: Header=BB2_1 Depth=1
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; V2-NEXT: subs r1, r1, r0
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; V2-NEXT: cmp r0, #0
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; V2-NEXT: bne .LBB2_1
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; V2-NEXT: .LBB2_4: @ %bb17
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; V2-NEXT: bx lr
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;
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; V3-LABEL: t2_nomerge:
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; V3: @ %bb.0: @ %entry
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; V3-NEXT: cmp r0, r1
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; V3-NEXT: beq .LBB2_4
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; V3-NEXT: b .LBB2_2
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; V3-NEXT: .LBB2_1: @ %cond_true
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; V3-NEXT: @ in Loop: Header=BB2_2 Depth=1
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; V3-NEXT: subs r0, r0, r1
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; V3-NEXT: cmp r1, r0
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; V3-NEXT: it eq
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; V3-NEXT: bxeq lr
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; V3-NEXT: .LBB2_2: @ %bb
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; V3-NEXT: @ =>This Inner Loop Header: Depth=1
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; V3-NEXT: cmp r0, r1
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; V3-NEXT: bgt .LBB2_1
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; V3-NEXT: @ %bb.3: @ %cond_false
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; V3-NEXT: @ in Loop: Header=BB2_2 Depth=1
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; V3-NEXT: subs r1, r1, r0
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; V3-NEXT: cmp r0, #0
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; V3-NEXT: bne .LBB2_2
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; V3-NEXT: .LBB2_4: @ %bb17
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; V3-NEXT: bx lr
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entry:
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; CHECK-LABEL: t2_nomerge:
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; CHECK-NOT: ite {{gt|le}}
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; CHECK-NOT: suble
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; CHECK-NOT: subgt
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%tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
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br i1 %tmp1434, label %bb17, label %bb.outer
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@ -104,6 +215,24 @@ bb17: ; preds = %cond_false, %cond_true, %entry
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@x = external global i32* ; <i32**> [#uses=1]
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define void @foo(i32 %a) nounwind {
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; V01-LABEL: foo:
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; V01: @ %bb.0: @ %entry
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; V01-NEXT: movw r1, :lower16:(L_x$non_lazy_ptr-(LPC3_0+4))
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; V01-NEXT: movt r1, :upper16:(L_x$non_lazy_ptr-(LPC3_0+4))
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; V01-NEXT: LPC3_0:
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; V01-NEXT: add r1, pc
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; V01-NEXT: ldr r1, [r1]
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; V01-NEXT: ldr r1, [r1]
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; V01-NEXT: str r0, [r1]
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; V01-NEXT: bx lr
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;
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; V23-LABEL: foo:
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; V23: @ %bb.0: @ %entry
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; V23-NEXT: movw r1, :lower16:x
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; V23-NEXT: movt r1, :upper16:x
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; V23-NEXT: ldr r1, [r1]
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; V23-NEXT: str r0, [r1]
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; V23-NEXT: bx lr
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entry:
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%tmp = load i32*, i32** @x ; <i32*> [#uses=1]
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store i32 %a, i32* %tmp
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@ -111,12 +240,29 @@ entry:
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}
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define void @t3(i32 %a, i32 %b) nounwind {
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; V01-LABEL: t3:
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; V01: @ %bb.0: @ %entry
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; V01-NEXT: cmp r0, #11
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; V01-NEXT: it lt
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; V01-NEXT: bxlt lr
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; V01-NEXT: LBB4_1: @ %cond_true
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; V01-NEXT: str lr, [sp, #-4]!
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; V01-NEXT: mov r0, r1
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; V01-NEXT: bl _foo
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; V01-NEXT: ldr lr, [sp], #4
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; V01-NEXT: bx lr
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;
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; V23-LABEL: t3:
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; V23: @ %bb.0: @ %entry
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; V23-NEXT: cmp r0, #11
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; V23-NEXT: it lt
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; V23-NEXT: bxlt lr
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; V23-NEXT: .LBB4_1: @ %cond_true
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; V23-NEXT: push {r7, lr}
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; V23-NEXT: mov r0, r1
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; V23-NEXT: bl foo
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; V23-NEXT: pop {r7, pc}
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entry:
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; CHECK-LABEL: t3:
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; CHECK: it lt
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; CHECK-NEXT: bxlt lr
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; CHECK: mov r0, r1
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; CHECK: bl {{_?}}foo
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%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
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br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
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@ -141,12 +141,18 @@ ASM_FUNCTION_ARM_MACHO_RE = re.compile(
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r'[ \t]*\.cfi_endproc\n',
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flags=(re.M | re.S))
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ASM_FUNCTION_THUMB_DARWIN_RE = re.compile(
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ASM_FUNCTION_THUMBS_DARWIN_RE = re.compile(
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r'^_(?P<func>[^:]+):\n'
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r'(?P<body>.*?)\n'
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r'[ \t]*\.data_region\n',
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flags=(re.M | re.S))
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ASM_FUNCTION_THUMB_DARWIN_RE = re.compile(
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r'^_(?P<func>[^:]+):\n'
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r'(?P<body>.*?)\n'
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r'^[ \t]*@[ \t]--[ \t]End[ \t]function',
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flags=(re.M | re.S))
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ASM_FUNCTION_ARM_IOS_RE = re.compile(
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r'^_(?P<func>[^:]+):\n'
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r'(?P<body>.*?)'
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@ -382,7 +388,8 @@ def get_run_handler(triple):
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'thumb': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE),
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'thumb-macho': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_MACHO_RE),
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'thumbv5-macho': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_MACHO_RE),
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'thumbv7s-apple-darwin' : (scrub_asm_arm_eabi, ASM_FUNCTION_THUMB_DARWIN_RE),
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'thumbv7s-apple-darwin' : (scrub_asm_arm_eabi, ASM_FUNCTION_THUMBS_DARWIN_RE),
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'thumbv7-apple-darwin' : (scrub_asm_arm_eabi, ASM_FUNCTION_THUMB_DARWIN_RE),
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'thumbv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE),
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'm68k': (scrub_asm_m68k, ASM_FUNCTION_M68K_RE),
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'mips': (scrub_asm_mips, ASM_FUNCTION_MIPS_RE),
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