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Author SHA1 Message Date
Jim Grosbach
01a937ac07 Remove dead code. These ARM instruction definitions no longer exist. 
llvm-svn: 127508
 2011-03-11 23:11:41 +00:00
Jim Grosbach
009af69d6d Pseudo-ize VMOVDcc and VMOVScc. 
llvm-svn: 127506
 2011-03-11 23:09:50 +00:00
Jim Grosbach
61ff87cd2d 80 columns 
llvm-svn: 127505
 2011-03-11 23:00:16 +00:00
Jim Grosbach
27eaca3e0d Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side- 
effect that we get proper instruction printing using the "pop" mnemonic for it.

llvm-svn: 127502
 2011-03-11 22:51:41 +00:00
Cameron Zwarich
bf5c9cd119 Roll r127459 back in: 
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127498
 2011-03-11 21:52:04 +00:00
Cameron Zwarich
39a49276db Fix the GCC test suite issue exposed by r127477, which was caused by stack 
protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.

llvm-svn: 127497
 2011-03-11 21:51:56 +00:00
Owen Anderson
78afadfa5d Teach FastISel to support register-immediate-immediate instructions. 
llvm-svn: 127496
 2011-03-11 21:33:55 +00:00
Jim Grosbach
39476d9010 80 columns. 
llvm-svn: 127495
 2011-03-11 21:02:27 +00:00
Jim Grosbach
4ed235527d Trailing whitespace. 
llvm-svn: 127493
 2011-03-11 20:59:19 +00:00
Jim Grosbach
b480da2317 Remove dead code. These ARM instruction definitions don't exist. 
llvm-svn: 127491
 2011-03-11 20:51:07 +00:00
Jim Grosbach
ee6075cda5 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same 
as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489
 2011-03-11 20:44:08 +00:00
Jim Grosbach
cb57d3b1d9 Remove dead code. These ARM instruction definitions don't exist. 
llvm-svn: 127488
 2011-03-11 20:38:18 +00:00
Jim Grosbach
3329263352 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q 
and VDUPLN32d, respectively.

llvm-svn: 127486
 2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d ARM VREV64df and VREV64qf can just be patterns. The instruction is the same 
as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485
 2011-03-11 20:18:05 +00:00
Jim Grosbach
fff6ff502b This FIXME has been fixed. 
llvm-svn: 127483
 2011-03-11 20:07:37 +00:00
Jim Grosbach
2ecded3a94 Properly pseudo-ize ARM MVNCCi. 
llvm-svn: 127482
 2011-03-11 19:55:55 +00:00
Jim Grosbach
9e8cf109dc Add missing 'return on failure'. Previously we'd crash after emitting 
the diagnostic.

llvm-svn: 127480
 2011-03-11 19:52:52 +00:00
Jan Sjödin
b58b9618ce Remove optimization emitting a reference insted of label difference, since it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used. 
llvm-svn: 127478
 2011-03-11 19:37:02 +00:00
Daniel Dunbar
a02706c889 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get 
created from the", it broke some GCC test suite tests.

llvm-svn: 127477
 2011-03-11 19:30:30 +00:00
Oscar Fuentes
548931d606 Force re-linking of LLVMgold.so when its exports file changes. 
llvm-svn: 127473
 2011-03-11 18:27:13 +00:00
Oscar Fuentes
d83646bbfd Fix processing of gold.exports. 
llvm-svn: 127471
 2011-03-11 18:07:46 +00:00
Devang Patel
8f39c0056d While printing annotations, print line number and variable name if debug info is present. 
llvm-svn: 127470
 2011-03-11 18:07:33 +00:00
Jim Grosbach
39804c0b44 Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4). 
llvm-svn: 127469
 2011-03-11 18:00:42 +00:00
Andrew Trick
6aa37a4a2b Replace -dag-chain-limit flag with constant. It has survived a release cycle without being touched, so no longer needs to pollute the hidden-help text. 
llvm-svn: 127468
 2011-03-11 17:46:59 +00:00
Oscar Fuentes
57a2625738 Add LTO and gold plugin to the CMake build. Linux-only, support for 
other systems pending.

PR9456.

llvm-svn: 127466
 2011-03-11 15:44:24 +00:00
Benjamin Kramer
d4ea449e7e ComputeMaskedBits: sub falls through to add, and sub doesn't have the same overflow semantics as add. 
Should fix the selfhost failures that started with r127463.

llvm-svn: 127465
 2011-03-11 14:46:49 +00:00
Benjamin Kramer
666407939f InstCombine: Fix a thinko where transform an icmp under the assumption that it's a zero comparison when it's not. 
Fixes PR9454.

llvm-svn: 127464
 2011-03-11 11:37:40 +00:00
Nick Lewycky
cf0e3e88df Teach ComputeMaskedBits about nsw on add. I don't think there's anything we can 
do with nuw here, but sub and mul should be given similar treatment.
Fixes PR9343 #15!

llvm-svn: 127463
 2011-03-11 09:00:19 +00:00
John Wiegley
e1168a569b Fix use of CompEnd predicate to be standards conforming 
The existing CompEnd predicate does not define a strict weak order as required
by the C++03 standard; therefore, its use as a predicate to std::upper_bound
is invalid. For a discussion of this issue, see
http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#270

This patch replaces the asymmetrical comparison with an iterator adaptor that
achieves the same effect while being strictly standard-conforming by ensuring
an apples-to-apples comparison.

llvm-svn: 127462
 2011-03-11 08:54:34 +00:00
Cameron Zwarich
9ed726c151 Optimize trivial branches in CodeGenPrepare, which often get created from the 
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127459
 2011-03-11 04:54:27 +00:00
Jim Grosbach
c7548fce48 Teach TableGen to pre-calculate register enum values when creating the 
CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.

rdar://9066491

llvm-svn: 127456
 2011-03-11 02:19:02 +00:00
Chris Lattner
2cd24b852f silence a conditional assignment -Wuninitialized warning. 
llvm-svn: 127453
 2011-03-11 02:12:51 +00:00
Jim Grosbach
6e41ec016b Make the register enum value part of the CodeGenRegister struct. 
llvm-svn: 127448
 2011-03-11 01:33:54 +00:00
Jim Grosbach
2c9ce71360 Trailing whitespace. 
llvm-svn: 127447
 2011-03-11 01:27:24 +00:00
Jim Grosbach
9834ed0ef4 Trailing whitespace. 
llvm-svn: 127446
 2011-03-11 01:19:05 +00:00
Jim Grosbach
9cddc3746d Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos. 
llvm-svn: 127445
 2011-03-11 01:16:49 +00:00
Jim Grosbach
ed45ac390c Properly pseudo-ize ARM MOVCCi and MOVCCi16. 
llvm-svn: 127442
 2011-03-11 01:09:28 +00:00
Eric Christopher
46f43c9cce Change the x86 32-bit scheduler to register pressure and fix up the 
corresponding testcases back to the previous versions.

Fixes some performance regressions only seen on 32-bit.

llvm-svn: 127441
 2011-03-11 01:05:58 +00:00
Evan Cheng
d5d2d4a158 Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613. 
llvm-svn: 127440
 2011-03-11 00:48:56 +00:00
Jim Grosbach
1986d9ac8f Properly pseudo-ize MOVCCr and MOVCCs. 
llvm-svn: 127434
 2011-03-10 23:56:09 +00:00
Dan Gohman
051cc738c3 RecursivelyDeleteTriviallyDeadInstructions only needs a 
Value, not an Instruction, so casting is not necessary. Also,
it's theoretically possible that the Value is not an
Instruction, since WeakVH follows RAUWs.

llvm-svn: 127427
 2011-03-10 20:57:44 +00:00
Rafael Espindola
222ccb2bdd Don't compute the file size if we don't need to. 
llvm-svn: 127426
 2011-03-10 20:54:07 +00:00
Dan Gohman
bb9c77f5bd Fix reassociate to postpone certain instruction deletions until 
after it has finished all of its reassociations, because its
habit of unlinking operands and holding them in a datastructure
while working means that it's not easy to determine when an
instruction is really dead until after all its regular work is
done. rdar://9096268.

llvm-svn: 127424
 2011-03-10 19:51:54 +00:00
Jim Grosbach
5891b1323a DMB can just be a pat referencing MCR. 
llvm-svn: 127423
 2011-03-10 19:27:17 +00:00
Jim Grosbach
4b74ef6ca9 Reorganize a bit. No functional change, just moving patterns up. 
llvm-svn: 127422
 2011-03-10 19:21:08 +00:00
Jim Grosbach
db549a7f6c Pseudo-instructions are codegenonly by definition. 
llvm-svn: 127420
 2011-03-10 19:06:39 +00:00
Jim Grosbach
41694b91ad Memory barrier instructions don't need special handling in tblgen anymore. 
llvm-svn: 127419
 2011-03-10 19:05:48 +00:00
Benjamin Kramer
52a44b9c80 InstCombine: Turn umul_with_overflow into mul nuw if we can prove that it cannot overflow. 
This happens a lot in clang-compiled C++ code because it adds overflow checks to operator new[]:
  unsigned *foo(unsigned n) { return new unsigned[n]; }
We can optimize away the overflow check on 64 bit targets because (uint64_t)n*4 cannot overflow.

llvm-svn: 127418
 2011-03-10 18:40:14 +00:00
Rafael Espindola
a271db1a12 Add r127409 back now that the windows file was updated. 
llvm-svn: 127417
 2011-03-10 18:33:29 +00:00
Rafael Espindola
11ae298b4f Try to fix the windows build. 
llvm-svn: 127416
 2011-03-10 18:30:48 +00:00