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Author SHA1 Message Date
Johnny Chen
359b9a2331 A7.3 register encoding 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

llvm-svn: 128949
 2011-04-05 22:57:07 +00:00
Johnny Chen
cf11408b65 ARM disassembler was erroneously accepting an invalid RSC instruction. 
Added checks for regs which should not be 15.

rdar://problem/9237734

llvm-svn: 128945
 2011-04-05 22:18:07 +00:00
Johnny Chen
6e1367d5dd ARM disassembler was erroneously accepting an invalid LSL instruction. 
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

llvm-svn: 128941
 2011-04-05 21:49:44 +00:00
Johnny Chen
b50ab34083 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. 
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873

llvm-svn: 128922
 2011-04-05 20:32:23 +00:00
Johnny Chen
4a15bdc1aa ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. 
llvm-svn: 128913
 2011-04-05 19:42:11 +00:00
Johnny Chen
f2d8c2ea3d LDRD now prints out two dst registers. 
llvm-svn: 128909
 2011-04-05 18:53:14 +00:00
Johnny Chen
d37098ae32 Constants with multiple encodings (ARM): 
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.

llvm-svn: 128897
 2011-04-05 18:02:46 +00:00
Johnny Chen
626c0a35f6 Check for invalid register encodings for UMAAL and friends where: 
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202

llvm-svn: 128895
 2011-04-05 17:43:10 +00:00
Johnny Chen
785ab1531b Fix SRS/SRSW encoding bits. 
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.

llvm-svn: 128864
 2011-04-05 00:16:18 +00:00
Johnny Chen
7fb247299a Fix incorrect alignment for NEON VST2b32_UPD. 
rdar://problem/9225433

llvm-svn: 128841
 2011-04-04 20:35:31 +00:00
Bruno Cardoso Lopes
74363376e4 - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT 
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

llvm-svn: 128832
 2011-04-04 17:18:19 +00:00
Joerg Sonnenberger
1cbd300346 Add support for the VIA PadLock instructions. 
llvm-svn: 128826
 2011-04-04 16:58:13 +00:00
Johnny Chen
dcd29e054c Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; 
instead of the second operand in addrmode_imm12.

rdar://problem/9225289

llvm-svn: 128757
 2011-04-02 02:24:54 +00:00
Johnny Chen
6f10cfdf01 Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. 
rdar://problem/9224276

llvm-svn: 128749
 2011-04-01 23:30:25 +00:00
Johnny Chen
b308662930 MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE. 
rdar://problem/9224120

llvm-svn: 128748
 2011-04-01 23:15:50 +00:00
Johnny Chen
845caa871c Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that 
all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094

llvm-svn: 128746
 2011-04-01 22:32:51 +00:00
Johnny Chen
65fe34ae00 Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction 
as invalid.

llvm-svn: 128734
 2011-04-01 20:21:38 +00:00
Johnny Chen
17f1f7c322 Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). 
rdar://problem/9219356

llvm-svn: 128722
 2011-04-01 18:26:38 +00:00
Bruno Cardoso Lopes
d285a7f27e Apply again changes to support ARM memory asm parsing. I removed 
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128689
 2011-03-31 23:26:08 +00:00
Johnny Chen
a7312b9622 Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which 
amounts to an UNDEFINED instruction.

llvm-svn: 128668
 2011-03-31 20:54:30 +00:00
Johnny Chen
2c5149791a Fix single word and unsigned byte data transfer instruction encodings so that 
Inst{4} = 0.

rdar://problem/9213022

llvm-svn: 128662
 2011-03-31 19:28:35 +00:00
Johnny Chen
0bb797b2f3 Add BLXi to the instruction table for disassembly purpose. 
A8.6.23 BLX (immediate)

rdar://problem/9212921

llvm-svn: 128644
 2011-03-31 17:53:50 +00:00
Daniel Dunbar
5827f55cc7 Remove stray empty test file. 
llvm-svn: 128640
 2011-03-31 17:01:56 +00:00
Bruno Cardoso Lopes
392dbfd384 Revert r128632 again, until I figure out what break the tests 
llvm-svn: 128635
 2011-03-31 15:54:36 +00:00
Bruno Cardoso Lopes
3b2f5421ac Reapply r128585 without generating a lib depedency cycle. An updated log: 
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128632
 2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
325e16f668 Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" 
This revision introduced a dependency cycle, as nlewycky mentioned by email.

llvm-svn: 128597
 2011-03-31 00:39:16 +00:00
Bruno Cardoso Lopes
cebbf7fe68 - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and 
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser

llvm-svn: 128585
 2011-03-30 23:32:32 +00:00
Johnny Chen
326082e0b2 Add a test case for thumb stc2 instruction. 
llvm-svn: 128517
 2011-03-30 01:02:06 +00:00
Kevin Enderby
976435fa83 Adding a test for "-inf" as well. 
llvm-svn: 128495
 2011-03-29 21:54:10 +00:00
Johnny Chen
28a32ef2d7 Add a test case for MSRi. 
llvm-svn: 128494
 2011-03-29 21:52:02 +00:00
Kevin Enderby
1ece39d99c Added support symbolic floating point constants in the MC assembler for Infinity 
and Nans with the same strings as GAS supports.  rdar://8673024

llvm-svn: 128488
 2011-03-29 21:11:52 +00:00
Johnny Chen
3c4cb78640 Add a thumb test file for printf (iOS 4.3). 
llvm-svn: 128487
 2011-03-29 21:09:30 +00:00
Johnny Chen
ab342ac374 A8.6.188 STC, STC2 
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.

rdar://problem/9200661

llvm-svn: 128478
 2011-03-29 19:49:38 +00:00
Johnny Chen
9a61664869 Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt. 
llvm-svn: 128477
 2011-03-29 19:10:06 +00:00
Johnny Chen
1cd323de0a Add and modify some tests. 
llvm-svn: 128476
 2011-03-29 19:08:52 +00:00
Owen Anderson
d73041e884 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist. 
llvm-svn: 128461
 2011-03-29 16:45:53 +00:00
Daniel Dunbar
5d8c7d0d36 MC: Add support for disabling "temporary label" behavior. Useful for debugging 
on Darwin.

llvm-svn: 128430
 2011-03-28 22:49:15 +00:00
Johnny Chen
8b921cebc6 Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. 
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.

llvm-svn: 128417
 2011-03-28 18:41:58 +00:00
Johnny Chen
61713b9c16 Fixed the t2PLD and friends disassembly and add two test cases. 
llvm-svn: 128322
 2011-03-26 01:32:48 +00:00
Johnny Chen
7238c61ff7 Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt. 
llvm-svn: 128306
 2011-03-25 23:02:58 +00:00
Johnny Chen
4c59e0a556 Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul(). 
llvm-svn: 128305
 2011-03-25 22:43:28 +00:00
Johnny Chen
75c4627aea Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID. 
Also add some test cases.

rdar://problem/9189829

llvm-svn: 128304
 2011-03-25 22:19:07 +00:00
Johnny Chen
5b840e19ef DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. 
rdar://problem/9182892

llvm-svn: 128299
 2011-03-25 19:35:37 +00:00
Johnny Chen
f16635a8f0 A8.6.226 TBB, TBH: 
Add two test cases.

llvm-svn: 128295
 2011-03-25 18:40:21 +00:00
Johnny Chen
c69c7b19ae Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to 
t2LDREX/t2STREX instructions.  Add two test cases.

llvm-svn: 128293
 2011-03-25 18:29:49 +00:00
Daniel Dunbar
1cbd2c6c88 MC: Improve some diagnostics on uses of '.' pseudo-symbol. 
llvm-svn: 128289
 2011-03-25 17:47:17 +00:00
Johnny Chen
f19366e37b Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that. 
rdar://problem/9184053

llvm-svn: 128285
 2011-03-25 17:31:16 +00:00
Johnny Chen
583b7cb25e Also need to handle invalid imod values for CPS2p. 
rdar://problem/9186136

llvm-svn: 128283
 2011-03-25 17:03:12 +00:00
Johnny Chen
1f29c2775d Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), 
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.

llvm-svn: 128252
 2011-03-25 01:09:48 +00:00
Johnny Chen
a4f73530a5 delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. 
llvm-svn: 128249
 2011-03-25 00:17:42 +00:00
Johnny Chen
4a55a733b8 The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since 
the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.

llvm-svn: 128247
 2011-03-24 23:42:31 +00:00
Johnny Chen
6345e6a882 The ARM disassembler was confused with the 16-bit tSTMIA instruction. 
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.

llvm-svn: 128246
 2011-03-24 23:21:14 +00:00
Johnny Chen
9672fe0126 Handle the added VBICiv*i* NEON instructions, too. 
llvm-svn: 128243
 2011-03-24 22:04:39 +00:00
Johnny Chen
1fc160fa19 T2 Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.

llvm-svn: 128240
 2011-03-24 21:36:56 +00:00
Benjamin Kramer
a9c4afdeec Plug a leak in the arm disassembler and put the tests back. 
llvm-svn: 128238
 2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
a5de5df6d8 Add asm parsing support w/ testcases for strex/ldrex family of instructions 
llvm-svn: 128236
 2011-03-24 21:04:58 +00:00
Johnny Chen
ef99d9b9eb Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'. 
These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.

llvm-svn: 128235
 2011-03-24 20:56:23 +00:00
Johnny Chen
ae5d27987a ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. 
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.

llvm-svn: 128234
 2011-03-24 20:42:48 +00:00
Johnny Chen
f6655e82b3 The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the 
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.

llvm-svn: 128226
 2011-03-24 18:40:38 +00:00
Johnny Chen
154393018f Add comments to the handling of opcode CPS3p to reject invalid instruction encoding, 
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.

llvm-svn: 128220
 2011-03-24 17:04:22 +00:00
Johnny Chen
404fb6c07f Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.

llvm-svn: 128191
 2011-03-24 01:40:42 +00:00
Johnny Chen
0d55ce3734 STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.

llvm-svn: 128189
 2011-03-24 01:07:26 +00:00
Johnny Chen
f8507c96f1 The r128103 fix to cope with the removal of addressing modes from the MC instructions 
were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.

llvm-svn: 128186
 2011-03-24 00:28:38 +00:00
Johnny Chen
b9309ecef1 Add disassembly test cases for: 
A8.6.292 VCMPE

llvm-svn: 128120
 2011-03-22 23:08:56 +00:00
Johnny Chen
beb7e880a2 LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.

This fixed http://llvm.org/bugs/show_bug.cgi?id=9530.

llvm-svn: 128113
 2011-03-22 22:28:49 +00:00
Johnny Chen
a31ae5ca74 Add one more test case for VFP Load/Store Multiple (vpop). 
llvm-svn: 128106
 2011-03-22 20:21:08 +00:00
Johnny Chen
90908a8eeb A8.6.399 VSTM: 
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions.  Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.

Also add a test case.

llvm-svn: 128103
 2011-03-22 20:00:10 +00:00
Rafael Espindola
b5c6ae67ac Write the section table and the section data in the same order that 
gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.

llvm-svn: 127972
 2011-03-20 18:44:20 +00:00
Johnny Chen
3520263009 Fixed an assert by the ARM disassembler for LDRD_PRE/POST. 
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand.  Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.

llvm-svn: 127935
 2011-03-19 01:16:20 +00:00
Owen Anderson
16fce7d4af Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. 
llvm-svn: 127917
 2011-03-18 22:50:18 +00:00
Joerg Sonnenberger
aa8ac259e9 Support explicit argument forms for the X86 string instructions. 
For now, only the default segments are supported.

llvm-svn: 127875
 2011-03-18 11:59:40 +00:00
Johnny Chen
14f091b6ab The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset. 
Remove the offending logic and update the test cases.

llvm-svn: 127843
 2011-03-18 00:38:03 +00:00
Johnny Chen
41abb5b0f7 It used to be that t_addrmode_s4 was used for both: 
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1

It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos).  Modify the
disassembler to reflect the change, and add relevant tests.

llvm-svn: 127833
 2011-03-17 22:04:05 +00:00
Daniel Dunbar
0e9d7aeb1f MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't have 
been removed.

llvm-svn: 127812
 2011-03-17 16:25:24 +00:00
Joerg Sonnenberger
e37bdf4386 Fix handling of @IDNTPOFF relocations, they need to get STT_TLS. 
While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too.

llvm-svn: 127780
 2011-03-17 00:35:10 +00:00
Johnny Chen
e88573849d There were two issues fixed: 
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
   Modify the ARMDisassemblerCore.cpp file to accomodate the change.

2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:

   imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
                                       // Encoding A1

   It has no business doing such.  Removed the offending logic.

Add test cases to arm-tests.txt.

llvm-svn: 127707
 2011-03-15 22:27:33 +00:00
Sean Callanan
e78b505311 Basic sanity checks to ensure that 2- and 3-byte 
VEX prefixes are working for triadic AVX
instructions.  This concludes the patch set to
enable AVX support for the X86 disassebler.

llvm-svn: 127647
 2011-03-15 01:32:46 +00:00
Johnny Chen
a86399b8e6 Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra 
register operand was erroneously added.  Remove an incorrect assert which triggers the bug.

rdar://problem/9131529

llvm-svn: 127642
 2011-03-15 01:13:17 +00:00
Cameron Zwarich
bf5c9cd119 Roll r127459 back in: 
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127498
 2011-03-11 21:52:04 +00:00
Daniel Dunbar
a02706c889 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get 
created from the", it broke some GCC test suite tests.

llvm-svn: 127477
 2011-03-11 19:30:30 +00:00
Cameron Zwarich
9ed726c151 Optimize trivial branches in CodeGenPrepare, which often get created from the 
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127459
 2011-03-11 04:54:27 +00:00
Johnny Chen
6bf5d7a170 LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. 
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16.  Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan

llvm-svn: 127354
 2011-03-09 20:01:14 +00:00
Bill Wendling
68934338ab * Correct encoding for VSRI. 
* Add tests for VSRI and VSLI.

llvm-svn: 127297
 2011-03-09 00:33:17 +00:00
Bill Wendling
b790c462c0 Correct the encoding for VRSRA and VSRA instructions. 
llvm-svn: 127294
 2011-03-09 00:00:35 +00:00
Bill Wendling
ab9f04b6d8 * Fix VRSHR and VSHR to have the correct encoding for the immediate. 
* Update the NEON shift instruction test to expect what 'as' produces.

llvm-svn: 127293
 2011-03-08 23:48:09 +00:00
Bill Wendling
0e4923ebe5 A few more tests for instruction encodings. 
llvm-svn: 127209
 2011-03-08 02:51:48 +00:00
Bill Wendling
958e854f40 Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 
expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
 2011-03-07 23:38:41 +00:00
Joerg Sonnenberger
5f2f5fa638 Be nice to Xcore and the XMOS assembler and avoid quoting section names 
that contain only letters, digits and the characters "_" and ".".

llvm-svn: 127028
 2011-03-04 20:03:14 +00:00
Eli Friedman
7243ca7572 Followup to r126970: add 64-bit encoding tests for str with reg operand. 
llvm-svn: 126987
 2011-03-04 04:06:47 +00:00
Eli Friedman
be07c34368 PR9377: Handle x86 str with register operand in a way consistent with gas. 
llvm-svn: 126970
 2011-03-04 00:10:17 +00:00
Joerg Sonnenberger
bb93506f95 Bug#9033: For the ELF assembler output, always quote the section name. 
llvm-svn: 126963
 2011-03-03 22:31:08 +00:00
Eli Friedman
f7eb4cce13 PR9352: Always emit a relocation for weak symbols. Not emitting relocations 
for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.

llvm-svn: 126933
 2011-03-03 07:24:36 +00:00
Bob Wilson
e24bee9ce8 TableGen should not ignore BX instructions for the ARM disassembler. pr9368. 
llvm-svn: 126931
 2011-03-03 07:19:52 +00:00
Bob Wilson
42f80596ca pr9367: Add missing predicated BLX instructions. 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915
 2011-03-03 01:41:01 +00:00
Kevin Enderby
58cc960338 Fixes an assertion failure while disassembling ARM rsbs reg/reg form. 
Patch by Ted Kremenek!

llvm-svn: 126895
 2011-03-02 23:08:33 +00:00
Bill Wendling
304dda7810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
Kevin Enderby
a1c2ea4ba0 Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.

llvm-svn: 126662
 2011-02-28 18:46:31 +00:00
Chris Lattner
90c8cff37e split this test into arch specific pieces, so the ARM 
test isn't run when the arm backend isn't built.  This
fixes PR9327

llvm-svn: 126500
 2011-02-25 19:06:35 +00:00
Joerg Sonnenberger
9c30c492df Restore r125595 (reverted in r126336) with modifications: 
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.

llvm-svn: 126443
 2011-02-24 21:59:22 +00:00
Devang Patel
bac565c8a3 Move arch specific tests in arch specific directories. 
llvm-svn: 126401
 2011-02-24 19:06:27 +00:00