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Commit Graph

216846 Commits

Author SHA1 Message Date
Philip Reames
03dfd6e443 [RS4GC] Treat inttoptr as base pointer
This is a modified version of a patch by tolziplohu with a style change, and most importantly, a revised commit message.

inttoptr for a non-integral address space is currently ill defined in the LangRef.  Figuring out exactly what the dynamic semantics of such a cast would be is hard, and not yet settled.  Despite that, we still need to go ahead and implement something in RS4GC for a couple of reasons.

First, as a simple consistency argument.  We're apparently added support for constexpr inttoptrs a while back, and even have tests which exercised them.  Having a lack of constant folding trigger a crash during lowering is non-ideal.

Second, and more fundementally, the optimizer is allowed to insert undefined constructs in unreachable code.  At the same time, we can't assume that dynamically dead code is always pruned before lowering.  As a result, we must assume that inttoptrs can occur (even if completely ill defined) along dead paths.  We need the lowering to not crash.  The stackmaps produced can be garbage (as the assumption is the code is dynamically dead), but the lowering itself can't crash.

Differential Revision: https://reviews.llvm.org/D103492
2021-06-07 10:27:23 -07:00
jasonliu
c03aed5d1b [XCOFF][AIX] Enable tooling support for 64 bit symbol table parsing
Add in the ability of parsing symbol table for 64 bit object.

Reviewed By: jhenderson, DiggerLin

Differential Revision: https://reviews.llvm.org/D85774
2021-06-07 17:24:13 +00:00
Sanjay Patel
30de816da1 [InstCombine] intersect nsz and ninf fast-math-flags (FMF) for fneg(fdiv) fold
https://alive2.llvm.org/ce/z/3KPvih

https://llvm.org/PR49654
2021-06-07 13:22:49 -04:00
Sanjay Patel
927aaff338 [InstCombine] refactor match clauses; NFC
We need to adjust the FMF propagation on at least
one of these transforms as discussed in:
https://llvm.org/PR49654
...so this should make it easier to intersect flags.
2021-06-07 13:22:49 -04:00
Sanjay Patel
2243b0992e [InstCombine] add tests for FMF propagation via -(C/X); NFC
There are bugs here as discussed in:
https://llvm.org/PR49654
2021-06-07 13:22:49 -04:00
Craig Topper
f4f2509f8a [RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.
This can cause the vectorizer to generate interleaved scalar
code which might be ok for some CPUs, but definitely not all.
Disable it to restore the previous scalar behavior.

Differential Revision: https://reviews.llvm.org/D103787
2021-06-07 10:20:59 -07:00
Tomasz Miąsko
181c195445 [Demangle][Rust] Parse instantiating crate
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D103460
2021-06-07 19:16:11 +02:00
Florian Hahn
46f03cce1a [VPlan] Print successors of VPRegionBlocks.
The non-DOT printing does not include the successors of VPregionBlocks.
This patch use the same style for printing successors as for
VPBasicBlock.

I think the printing of successors could be a bit improved further, as
at the moment it is hard to ensure a check line matches all successors.
But that can be done as follow-up.

Reviewed By: a.elovikov

Differential Revision: https://reviews.llvm.org/D103515
2021-06-07 17:57:21 +01:00
Krzysztof Parzyszek
a4d9276f53 [docs] Set Phabricator as the tool for pre-commit reviews
Differential Revision: https://reviews.llvm.org/D103811
2021-06-07 11:50:52 -05:00
Raphael Isemann
001e5b68a5 [NFC] Add missing include to LaneBitmask.h to fix modules build 2021-06-07 18:43:00 +02:00
Sander de Smalen
c2092c7f0d [CostModel][AArch64] NFC: Simplify some cost model tests for SVE.
* Merged some functions into a single function, to make the costs more obvious.
* Moved scalable-mem-op-cost-model.ll -> sve-ldst.ll to be more consistent with other filenames.
2021-06-07 17:26:23 +01:00
Sander de Smalen
052444882c [CostModel] Return Invalid cost in getArithmeticCost instead of crashing for scalable vectors.
This fixes an issue in BasicTTIImpl.h where it tries to do a
cast<FixedVectorType> on a scalable vector type in order to get the
scalarization cost. Because scalarization of scalable vectors is not
supported, we return Invalid instead.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103798
2021-06-07 17:26:23 +01:00
Tomasz Miąsko
1d2a2e625f [Demangle][Rust] Parse dyn-trait-assoc-binding
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D103364
2021-06-07 18:18:31 +02:00
Tomasz Miąsko
5534f83077 [Demangle][Rust] Parse dyn-trait
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D103361
2021-06-07 18:18:31 +02:00
Tomasz Miąsko
5d985b77fe [Demangle][Rust] Parse dyn-bounds
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D103151
2021-06-07 18:18:30 +02:00
Fraser Cormack
d90162a00a [InstCombine] Support negation of scalable-vector splats
This patch is an extension of D103421. It allows the InstCombiner to
generate the negated form of integer scalable-vector splats. It can
technically handle fixed-length vectors too but those are completely
covered by the preceding logic.

This enables extra combining opportunities for scalable vector types.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103801
2021-06-07 15:14:00 +01:00
Sebastian Neubauer
38d0179c03 [AMDGPU] Use s_add_i32 for address additions
This allows to convert the add instruction to s_addk_i32 and
v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU
instruction.

Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 16:09:48 +02:00
Abhina Sreeskantharajan
a86aa7478c [test] Use host platform specific error message substitution
This testcase is failing on z/OS because the regex doesn't match the spelling. This patch modifies the testcase to use the error substitution so it will pass on all platforms.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D103804
2021-06-07 10:06:38 -04:00
Fraser Cormack
30fb60dd84 [Constants] Extend support for scalable-vector splats
This patch extends the various "isXXX" functions of the `Constant` class
to include scalable-vector splats.

In several "isXXX" functions, code that was separately inspecting
`ConstantVector` and `ConstantDataVector` was unified to use
`getSplatValue`, which already includes support for said splats.

In the varous "isNotXXX" functions, code was added to check whether the
scalar splat value -- if any -- satisfies the predicate.

An extra fix for `isNotMinSignedValue` was included, as it previously
crashed when passed a scalable-vector type because it unconditionally
cast to `FixedVectorType`

These changes address numerous missed optimizations, a compiler crash
mentioned above and -- perhaps most egregiously -- an infinite loop in
InstCombine due to the compiler breaking canonical form when it failed
to pick up on a splat in a select instruction.

Test cases have been added to cover as many of these functions as
possible, though existing coverage is slim; it doesn't appear that there
are any in-tree uses of `Constant::isNegativeZeroValue`, for example.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103421
2021-06-07 14:37:56 +01:00
hsmahesha
7520c18108 [AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering.
Before packing LDS globals into a sorted structure, make sure that
their alignment is properly updated based on their size. This will make
sure that the members of sorted structure are properly aligned, and
hence it will further reduce the probability of unaligned LDS access.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D103261
2021-06-07 18:00:41 +05:30
Daniil Seredkin
a94c7622c5 [InstCombine] Missed optimization for pow(x, y) * pow(x, z) with fast-math
If FP reassociation (fast-math) is allowed, then LLVM is free to do the
following transformation pow(x, y) * pow(x, z) -> pow(x, y + z).
This patch adds this transformation and tests for it.
See more https://bugs.llvm.org/show_bug.cgi?id=47205

It handles two cases

1. When operands of fmul are different instructions

%4 = call reassoc float @llvm.pow.f32(float %0, float %1)
%5 = call reassoc float @llvm.pow.f32(float %0, float %2)
%6 = fmul reassoc float %5, %4
-->
%3 = fadd reassoc float %1, %2
%4 = call reassoc float @llvm.pow.f32(float %0, float %3)

2. When operands of fmul are the same instruction

%4 = call reassoc float @llvm.pow.f32(float %0, float %1)
%5 = fmul reassoc float %4, %4
-->
%3 = fadd reassoc float %1, %1
%4 = call reassoc float @llvm.pow.f32(float %0, float %3)

Differential Revision: https://reviews.llvm.org/D102574
2021-06-07 08:08:05 -04:00
Nico Weber
52fe7939d4 [gn build] fix syntax error from 50bb1b930dbc 2021-06-07 07:27:58 -04:00
Bradley Smith
6fa37c2af6 [AArch64][SVE] Improve codegen for dupq SVE ACLE intrinsics
Use llvm.experimental.vector.insert instead of storing into an alloca
when generating code for these intrinsics. This defers the codegen of
the generated vector to instruction selection, allowing existing
shufflevector style optimizations to apply.

Additionally, introduce a new target transform that can recognise fixed
predicate patterns in the svbool variants of these intrinsics.

Differential Revision: https://reviews.llvm.org/D103082
2021-06-07 12:21:38 +01:00
Florian Hahn
0857586425 [LV] Update more target-specific tests after 23c2f2e6b24d. 2021-06-07 12:13:21 +01:00
Florian Hahn
be17b181ce [Matrix] Add -matrix-allow-contract=false to tests.
Explicitly specify contract behavior, so the tests are independent of
the current default of the flag.
2021-06-07 12:13:20 +01:00
Liqiang Tao
a80254f9ba [llvm] Add interface to order inlining
This patch abstract Calls in Inliner:run() to InlineOrder.
With this patch, it's possible to customize the inlining order,
e.g. use queue or priority queue.

Reviewed By: kazu

Differential Revision: https://reviews.llvm.org/D103315
2021-06-07 18:27:55 +08:00
Guillaume Chatelet
517914e3e7 [NFC] Fix semantic discrepancy for MVT::LAST_VALUETYPE
Differential Revision: https://reviews.llvm.org/D103251
2021-06-07 10:04:16 +00:00
Florian Hahn
b239ef54b6 [PhaseOrdering] Update tests after 23c2f2e6b24d. 2021-06-07 10:59:30 +01:00
Jingu Kang
7721ad79a0 [SimpleLoopBoundSplit] Split Bound of Loop which has conditional branch with IV
This pass transforms loops that contain a conditional branch with induction
variable. For example, it transforms left code to right code:

                             newbound = min(n, c)
 while (iv < n) {            while(iv < newbound) {
   A                           A
   if (iv < c)                 B
     B                         C
   C                         }
 }                           if (iv != n) {
                               while (iv < n) {
                                 A
                                 C
                               }
                             }

Differential Revision: https://reviews.llvm.org/D102234
2021-06-07 10:55:25 +01:00
Florian Hahn
3f021fa672 [LV] Mark increment of main vector loop induction variable as NUW.
This patch marks the induction increment of the main induction variable
of the vector loop as NUW when not folding the tail.

If the tail is not folded, we know that End - Start >= Step (either
statically or through the minimum iteration checks). We also know that both
Start % Step == 0 and End % Step == 0. We exit the vector loop if %IV +
%Step == %End. Hence we must exit the loop before %IV + %Step unsigned
overflows and we can mark the induction increment as NUW.

This should make SCEV return more precise bounds for the created vector
loops, used by later optimizations, like late unrolling.

At the moment quite a few tests still need to be updated, but before
doing so I'd like to get initial feedback to make sure I am not missing
anything.

Note that this could probably be further improved by using information
from the original IV.

Attempt of modeling of the assumption in Alive2:
https://alive2.llvm.org/ce/z/H_DL_g

Part of a set of fixes required for PR50412.

Reviewed By: mkazantsev

Differential Revision: https://reviews.llvm.org/D103255
2021-06-07 10:47:52 +01:00
Jay Foad
6be6937d0c [AMDGPU] Fix MC tests for v_fmaak_f16 and v_fmamk_f16
This looks like a mistake when the tests were committed in r363946.
There were two sets of tests for the f32 variant of these instructions,
instead of one set for f16 and one set for f32.

Differential Revision: https://reviews.llvm.org/D103699
2021-06-07 10:42:52 +01:00
Esme-Yi
4f2a658209 Fixed the build failure of yaml2obj in XCOFFEmitter.cpp:
error: ambiguous overload for 'operator=='
  (operand types are 'llvm::yaml::Hex16' and 'llvm::XCOFF::MagicNumber')
     Is64Bit = Obj.Header.Magic == XCOFF::XCOFF64;
2021-06-07 05:45:05 +00:00
Esme-Yi
4a3c52750c [yaml2obj] Initial the support of yaml2obj for 32-bit XCOFF.
Summary: The patch implements the mapping of the Yaml
information to XCOFF object file to enable the yaml2obj
tool for XCOFF. Currently only 32-bit is supported.

Reviewed By: jhenderson, shchenz

Differential Revision: https://reviews.llvm.org/D95505
2021-06-07 04:14:44 +00:00
Simon Pilgrim
779c968967 [CostModel][X86] Add 512-bit bswap costs 2021-06-06 22:36:34 +01:00
Simon Pilgrim
3d3fded81f [CostModel][X86] Add 512-bit bswap cost tests 2021-06-06 22:36:34 +01:00
David Green
f44fcc3cc0 [ARM] MVE tests for vmull from a splat. NFC 2021-06-06 22:30:02 +01:00
David Green
a4d05be9e6 [AArch64] Extra tests for vector shift. NFC 2021-06-06 22:29:44 +01:00
Simon Pilgrim
3d02a9f278 [CostModel][X86] Improve AVX512 FDIV costs
Add missing v16f32/v8f64 costs and adjust other costs as well based off the SkylakeServer model
2021-06-06 21:41:05 +01:00
Craig Topper
b18ef7f90e [RISCV] Replace && with ||. Spotted by coverity.
We should be exiting when the shift amount is greater than
the bit width regardless of whether it is a power of 2.

Reported by Simon Pilgrim here https://reviews.llvm.org/D96661

This requires getting a shift amount that is out of bounds that
wasn't already optimized by SelectionDAG. This would be pretty
trick to construct a test for.

Or it would require a non-power of 2 shift amount and a mask
that has runs of ones and zeros of the next lowest power of 2 from
that shift amount. I tried a little to produce a test for this,
but didn't get it to work.
2021-06-06 13:09:51 -07:00
Simon Pilgrim
0e6ebc4153 [X86][SSE] LowerFP_TO_INT - remove dead code. NFCI.
Non-Strict v2f32->v2i64 cases have already early-returned to be handled by legalization.
2021-06-06 20:04:15 +01:00
Simon Pilgrim
2cad20b386 [X86][SSE] combineVectorTruncation - simplify PSHUFB-is-better logic. NFCI.
OutSVT is guaranteed to be i8/i16 and we accept any InSVT that isn't i64
2021-06-06 20:04:14 +01:00
maekawatoshiki
c253e5477f Revert "[LoopUnrollAndJam] Change LoopUnrollAndJamPass to LoopNest pass"
This reverts commit 21653600034084e8335374ddc1eb8d362158d9a8.

To fix the crash problem in legacy pass manager
2021-06-07 01:26:47 +09:00
Simon Pilgrim
ee630c4d10 X86MachObjectWriter.cpp - silence null deference warnings. NFCI.
The MCSymbol data should always be present for non-absolute sections so assert that it is to silence static analysis warnings.
2021-06-06 15:33:47 +01:00
Nikita Popov
6fa17c5cd4 [TargetLowering] Use IRBuilderBase instead of IRBuilder<> (NFC)
Don't require a specific kind of IRBuilder for TargetLowering hooks.
This allows us to drop the IRBuilder.h include from TargetLowering.h.

Differential Revision: https://reviews.llvm.org/D103759
2021-06-06 16:29:50 +02:00
Nikita Popov
7503a24bcc [LexicalScopesTest] Add missing IRBuilder.h include (NFC)
This currently depends on a transitive include via TargetLowering.h.
2021-06-06 16:29:50 +02:00
Simon Pilgrim
1271ac390e X86Operand.h - fix uninitialized variable warnings in constructor. NFCI. 2021-06-06 15:25:03 +01:00
Simon Pilgrim
7d37c257aa AssumeBundleQueries.cpp - don't dereference a dyn_cast<> result. NFCI.
Use cast<> instead which will assert that the cast is correct and not just return null - the match() should have already failed if the cast isn't valid anyhow.

Fixes static analysis warning.
2021-06-06 15:25:03 +01:00
Nikita Popov
435f6cc870 [TargetLowering] Move methods out of line (NFC)
Move methods using IRBuilder out of line, so we can drop the
dependency on the header.
2021-06-06 16:02:10 +02:00
Nikita Popov
a84c0ba160 [CodeGen] Add missing includes (NFC)
These currently rely on the IRBuilder.h include in TargetLowering.h.
Make them explicit.
2021-06-06 15:48:27 +02:00
Simon Pilgrim
0f776c6eda SimplifyCFG.cpp - remove dead early-return code added at rGcc63203908da. NFCI.
We've already checked that ScanIdx == 0 a few lines above.
2021-06-06 14:15:11 +01:00