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276 Commits

Author SHA1 Message Date
Evan Cheng
ca5eaf4020 Avoid getting into an infinite loop when -disable-x86-shuffle-opti is specified. 
llvm-svn: 30974
 2006-10-16 06:36:00 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Evan Cheng
d07e2f081a Some X86ISD::CMP were created with wrong ValueType's. 
llvm-svn: 30913
 2006-10-12 19:12:56 +00:00
Evan Cheng
8f6c6b19e6 Don't convert to MOVLP if using shufps etc. may allow load folding. 
llvm-svn: 30847
 2006-10-09 21:39:25 +00:00
Evan Cheng
d22f3dd3ed Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Evan Cheng
275825195a Make use of getStore(). 
llvm-svn: 30759
 2006-10-05 23:01:46 +00:00
Chris Lattner
7f98896c02 Lower some min/max idioms to minss/maxss when unsafe fp math is enabled. 
llvm-svn: 30748
 2006-10-05 04:11:26 +00:00
Evan Cheng
a77dd83caf Added option -disable-x86-shuffle-opti to disable X86 specific vector shuffle optimizations. 
llvm-svn: 30723
 2006-10-04 18:33:38 +00:00
Chris Lattner
4ec6c298d8 Pattern match min/max nodes when we have sse. This implements 
CodeGen/X86/scalar_sse_minmax.ll

llvm-svn: 30719
 2006-10-04 06:57:07 +00:00
Evan Cheng
494e8e6971 Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an 
extra operand to LOADX to specify the exact value extension type.

llvm-svn: 30714
 2006-10-04 00:56:09 +00:00
Chris Lattner
72276ae651 Fix PR933 and CodeGen/X86/2006-10-02-BoolRetCrash.ll 
llvm-svn: 30703
 2006-10-03 17:18:42 +00:00
Chris Lattner
0501525c0e silence warnings in release build 
llvm-svn: 30631
 2006-09-27 18:29:38 +00:00
Chris Lattner
b826d65e01 Various random and minor code cleanups. 
llvm-svn: 30608
 2006-09-26 03:57:53 +00:00
Nick Lewycky
401794f2a7 Fix compile error. 
llvm-svn: 30553
 2006-09-21 02:08:31 +00:00
Anton Korobeynikov
59ef7e94eb Adding codegeneration for StdCall & FastCall calling conventions 
llvm-svn: 30549
 2006-09-20 22:03:51 +00:00
Anton Korobeynikov
7c2118575c Added some eye-candy for Subtarget type checking 
Added X86 StdCall & FastCall calling conventions. Codegen will follow.

llvm-svn: 30446
 2006-09-17 20:25:45 +00:00
Anton Korobeynikov
b2b7c2f8b9 Small fixes for supporting dll* linkage types 
llvm-svn: 30441
 2006-09-17 13:06:18 +00:00
Anton Korobeynikov
6e19f80688 Adding dllimport, dllexport and external weak linkage types. 
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.

llvm-svn: 30374
 2006-09-14 18:23:27 +00:00
Chris Lattner
5a00b32eec Turn X < 0 -> TEST X,X js 
llvm-svn: 30294
 2006-09-13 17:04:54 +00:00
Chris Lattner
d2b6dcd4bf The sense of this branch was inverted :( 
llvm-svn: 30293
 2006-09-13 16:56:12 +00:00
Chris Lattner
806ef17e5b Compile X > -1 -> text X,X; js dest 
This implements CodeGen/X86/jump_sign.ll.

llvm-svn: 30283
 2006-09-13 03:22:10 +00:00
Evan Cheng
dd52a60189 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Evan Cheng
cfd7b147cf X86ISD::CMP now produces a chain as well as a flag. Make that the chain 
operand of a conditional branch to allow load folding into CMP / TEST
instructions.

llvm-svn: 30241
 2006-09-11 02:19:56 +00:00
Evan Cheng
15dd42884e Committing X86-64 support. 
llvm-svn: 30177
 2006-09-08 06:48:29 +00:00
Evan Cheng
da0f93c5af - Identify a vector_shuffle that can be turned into an undef, e.g. 
shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
  optimal code by failing to identify MOVL (move to lowest element of a
  vector).

llvm-svn: 30171
 2006-09-08 01:50:06 +00:00
Chris Lattner
9c7673ffca Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns 
using test, which provides nice simplifications like:

-       movl %edi, %ecx
-       andl $2, %ecx
-       cmpl $0, %ecx
+       testl $2, %edi
        je LBB1_11      #cond_next90

There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.

llvm-svn: 30156
 2006-09-07 20:33:45 +00:00
Chris Lattner
f92824aa27 Revert this patch, the front-end has been fixed to make it unneccesary. 
llvm-svn: 29752
 2006-08-17 18:43:24 +00:00
Chris Lattner
989f26b766 'g' is handled by the front-end. 
llvm-svn: 29751
 2006-08-17 18:12:28 +00:00
Andrew Lenharth
e720e5c444 Fix handling of 'g'. Closes 883 
llvm-svn: 29750
 2006-08-17 17:50:12 +00:00
Andrew Lenharth
bea8a84eb1 Add the 'c' constraint as needed by the linux kernel 
llvm-svn: 29747
 2006-08-17 16:07:50 +00:00
Andrew Lenharth
7fdc3bbbcf Add support for S and D constraints, as needed to compile the linux kernel. 
llvm-svn: 29746
 2006-08-17 15:35:43 +00:00
Chris Lattner
8ca6e82bce Eliminate use of getNode that takes a vector. 
llvm-svn: 29614
 2006-08-11 17:38:39 +00:00
Evan Cheng
6053206580 Match tablegen changes. 
llvm-svn: 29604
 2006-08-11 09:08:15 +00:00
Evan Cheng
131c832304 Convert more calls of getNode() that takes a vector to pass in the start of an array. 
llvm-svn: 29601
 2006-08-11 07:35:45 +00:00
Chris Lattner
7b1362fa52 Start eliminating temporary vectors used to create DAG nodes. Instead, pass 
in the start of an array and a count of operands where applicable.  In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap.  In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.

I updated a lot of code calling getNode that takes a vector, but ran out of
time.  The rest of the code should be updated, and these methods should be
removed.

We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.

It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.

llvm-svn: 29566
 2006-08-08 02:23:42 +00:00
Chris Lattner
26ff12f7f5 Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll. 
The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.

llvm-svn: 29420
 2006-07-31 23:26:50 +00:00
Chris Lattner
b4165c39d7 Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC. 
llvm-svn: 29307
 2006-07-26 21:12:04 +00:00
Evan Cheng
ed1c019899 This opt is now handled in DAG combine. 
llvm-svn: 29243
 2006-07-21 08:26:46 +00:00
Evan Cheng
56434b7578 A splat of a vector constant of all zero or all one is the vector constant. 
llvm-svn: 29234
 2006-07-20 23:09:47 +00:00
Chris Lattner
d0202bbed3 Add information preventing several register class constraints from working. 
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll

llvm-svn: 29118
 2006-07-12 16:59:49 +00:00
Chris Lattner
b75fe307e1 Implement the inline asm 'A' constraint. This implements PR825 and 
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll

llvm-svn: 29101
 2006-07-11 02:54:03 +00:00
Evan Cheng
b5e6a4a74d Fixed stack objects do not specify alignments, but their offsets are known. 
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.

llvm-svn: 29090
 2006-07-10 21:37:44 +00:00
Chris Lattner
18c77b92a9 Mark internal function static 
llvm-svn: 29085
 2006-07-10 19:53:12 +00:00
Evan Cheng
1d48a494a2 X86 target specific DAG combine: turn build_vector (load x), (load x+4), 
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).

e.g.

__m128 test(float a, float b, float c, float d) {
  return _mm_set_ps(d, c, b, a);
}

_test:
        movups 4(%esp), %xmm0
        ret

llvm-svn: 29042
 2006-07-07 08:33:52 +00:00
Evan Cheng
801ea78096 Reorg. No functionality change. 
llvm-svn: 28999
 2006-07-05 22:17:51 +00:00
Evan Cheng
db5c7909f5 Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary. 
llvm-svn: 28910
 2006-06-24 08:36:10 +00:00
Evan Cheng
bc79e5f0e4 Type of vector extract / insert index operand should be iPTR. 
llvm-svn: 28796
 2006-06-15 08:14:54 +00:00
Evan Cheng
242ebc9ab3 Add argument registers to the end of call operand list (partial fix). 
llvm-svn: 28783
 2006-06-14 18:17:40 +00:00
Evan Cheng
8f46dba83d Minor compilation speed improvement. 
llvm-svn: 28736
 2006-06-09 06:24:42 +00:00
Evan Cheng
2da9d803a4 Added X86FunctionInfo subclass of MachineFunction to record whether the 
function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.

llvm-svn: 28703
 2006-06-06 23:30:24 +00:00