RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 13:33:37 +02:00
Code Issues Projects Releases Wiki Activity
14,674 Commits 4 Branches 5 Tags 704 MiB
04cb07f3ce
Commit Graph

319 Commits

Author SHA1 Message Date
Reid Spencer
1b7459b29d Initial version of automake Makefile.am file. 
llvm-svn: 16893
 2004-10-10 22:20:40 +00:00
Chris Lattner
6ff0fd4837 bling bling! 
llvm-svn: 16873
 2004-10-10 16:26:13 +00:00
Nate Begeman
dfefd2f3fc Implement logical and with an immediate that consists of a contiguous block 
of one or more 1 bits (may wrap from least significant bit to most
significant bit) as the rlwinm rather than andi., andis., or some longer
instructons sequence.

int andn4(int z) { return z & -4; }
int clearhi(int z) { return z & 0x0000FFFF; }
int clearlo(int z) { return z & 0xFFFF0000; }
int clearmid(int z) { return z & 0x00FFFF00; }
int clearwrap(int z) { return z & 0xFF0000FF; }

_andn4:
        rlwinm r3, r3, 0, 0, 29
        blr

_clearhi:
        rlwinm r3, r3, 0, 16, 31
        blr

_clearlo:
        rlwinm r3, r3, 0, 0, 15
        blr

_clearmid:
        rlwinm r3, r3, 0, 8, 23
        blr

_clearwrap:
        rlwinm r3, r3, 0, 24, 7
        blr

llvm-svn: 16832
 2004-10-08 02:49:24 +00:00
Nate Begeman
370b1b7a9a Several fixes and enhancements to the PPC32 backend. 
1. Fix an illegal argument to getClassB when deciding whether or not to
   sign extend a byte load.

2. Initial addition of isLoad and isStore flags to the instruction .td file
   for eventual use in a scheduler.

3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
   that we can emit the PowerPC shifted immediate instructions far more
   often.  This allows us to emit the following code:

int foo(int x) { return x | 0x00F0000; }

_foo:
.LBB_foo_0:     ; entry
        ; IMPLICIT_DEF
        oris r3, r3, 15
        blr

llvm-svn: 16826
 2004-10-07 22:30:03 +00:00
Nate Begeman
76d2a77998 Add ori reg, reg, 0 as a move instruction. This can be generated from 
loading a 32bit constant into a register whose low halfword is all zeroes.

We now omit the ori after the lis for the following C code:

int bar(int y) { return y * 0x00F0000; }

_bar:
.LBB_bar_0:     ; entry
        ; IMPLICIT_DEF
        lis r2, 15
        mullw r3, r3, r2
        blr

llvm-svn: 16825
 2004-10-07 22:26:12 +00:00
Nate Begeman
f60feea650 Remove unnecessary header include 
llvm-svn: 16824
 2004-10-07 22:24:32 +00:00
Chris Lattner
38fbf09104 Correct some typeos 
llvm-svn: 16770
 2004-10-06 16:28:24 +00:00
Nate Begeman
79d42a185e Turning on fsel code gen now that we can do so would be good. 
llvm-svn: 16765
 2004-10-06 11:03:30 +00:00
Nate Begeman
7b4fe83ba8 Implement floating point select for lt, gt, le, ge using the powerpc fsel 
instruction.

Now, rather than emitting the following loop out of bisect:
.LBB_main_19:	; no_exit.0.i
	rlwinm r3, r2, 3, 0, 28
	lfdx f1, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f2, f2, f1
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
	fcmpu cr0, f1, f4
	bge .LBB_main_64	; no_exit.0.i
.LBB_main_63:	; no_exit.0.i
	b .LBB_main_65	; no_exit.0.i
.LBB_main_64:	; no_exit.0.i
	fmr f2, f1
.LBB_main_65:	; no_exit.0.i
	addi r3, r2, 1
	rlwinm r3, r3, 3, 0, 28
	lfdx f1, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f4, f4, f1
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3)
	fcmpu cr0, f1, f5
	bge .LBB_main_67	; no_exit.0.i
.LBB_main_66:	; no_exit.0.i
	b .LBB_main_68	; no_exit.0.i
.LBB_main_67:	; no_exit.0.i
	fmr f4, f1
.LBB_main_68:	; no_exit.0.i
	fadd f1, f2, f4
	addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
	lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
	fmul f1, f1, f2
	rlwinm r3, r2, 3, 0, 28
	lfdx f2, r3, r28
	fadd f4, f2, f1
	fcmpu cr0, f4, f0
	bgt .LBB_main_70	; no_exit.0.i
.LBB_main_69:	; no_exit.0.i
	b .LBB_main_71	; no_exit.0.i
.LBB_main_70:	; no_exit.0.i
	fmr f0, f4
.LBB_main_71:	; no_exit.0.i
	fsub f1, f2, f1
	addi r2, r2, -1
	fcmpu cr0, f1, f3
	blt .LBB_main_73	; no_exit.0.i
.LBB_main_72:	; no_exit.0.i
	b .LBB_main_74	; no_exit.0.i
.LBB_main_73:	; no_exit.0.i
	fmr f3, f1
.LBB_main_74:	; no_exit.0.i
	cmpwi cr0, r2, -1
	fmr f16, f0
	fmr f17, f3
	bgt .LBB_main_19	; no_exit.0.i

We emit this instead:
.LBB_main_19:	; no_exit.0.i
	rlwinm r3, r2, 3, 0, 28
	lfdx f1, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f2, f2, f1
	fsel f1, f1, f1, f2
	addi r3, r2, 1
	rlwinm r3, r3, 3, 0, 28
	lfdx f2, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f4, f4, f2
	fsel f2, f2, f2, f4
	fadd f1, f1, f2
	addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
	lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
	fmul f1, f1, f2
	rlwinm r3, r2, 3, 0, 28
	lfdx f2, r3, r28
	fadd f4, f2, f1
	fsub f5, f0, f4
	fsel f0, f5, f0, f4
	fsub f1, f2, f1
	addi r2, r2, -1
	fsub f2, f1, f3
	fsel f3, f2, f3, f1
	cmpwi cr0, r2, -1
	fmr f16, f0
	fmr f17, f3
	bgt .LBB_main_19	; no_exit.0.i

llvm-svn: 16764
 2004-10-06 09:53:04 +00:00
Nate Begeman
65376f660e Generate better code by being far less clever when it comes to the select instruction. Don't create overlapping register lifetimes 
llvm-svn: 16580
 2004-09-29 05:00:31 +00:00
Nate Begeman
a8b079e16a improve Type::BoolTy codegen by eliminating unnecessary clears and sign extends 
llvm-svn: 16578
 2004-09-29 03:45:33 +00:00
Nate Begeman
dc50ea0d82 To go along with sabre's improved InstCombining, improve recognition of 
integers that we can use as immediate values in instructions.

Example from yacr2:
-       lis r10, -1
-       ori r10, r10, 65535
-       add r28, r28, r10
+       addi r28, r28, -1
        addi r7, r7, 1
        addi r9, r9, 1
        b .LBB_main_9   ; loopentry.1.i214

llvm-svn: 16566
 2004-09-29 02:35:05 +00:00
Nate Begeman
921a44443d Correct some BuildMI arguments for the upcoming simple scheduler 
llvm-svn: 16519
 2004-09-27 05:08:17 +00:00
Nate Begeman
75f0d35dc6 Fix the last of the major PPC GEP folding deficiencies. This will allow 
the ISel to use indexed and non-zero immediate offsets for GEPs that have
more than one use.  This is common for instruction sequences such as a load
followed by a modify and store to the same address.

llvm-svn: 16493
 2004-09-23 05:31:33 +00:00
Nate Begeman
61d1797c03 add optimized code sequences for setcc x, 0 
llvm-svn: 16478
 2004-09-22 04:40:25 +00:00
Misha Brukman
bd9f406b0b s/ISel/PPC64ISel/ to have unique class names for debugging via gdb because the 
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.

llvm-svn: 16471
 2004-09-21 18:22:33 +00:00
Misha Brukman
6ad6dd2ab9 s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because the 
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.

llvm-svn: 16470
 2004-09-21 18:22:19 +00:00
Chris Lattner
aee36bb527 Revamp the Register class, and allow the use of the RegisterGroup class to 
specify aliases directly in register definitions.

Patch contributed by Jason Eckhardt!

llvm-svn: 16330
 2004-09-14 04:17:02 +00:00
Nate Begeman
ce6d62eac7 Add 64 bit divide instructions, and use them 
llvm-svn: 16198
 2004-09-06 18:46:59 +00:00
Misha Brukman
8e6e187922 * Change PPC32AsmPrinter => PowerPCAsmPrinter since it is now shared between 
Darwin and AIX and is not 32- or 64-bit specific
* Bring back PowerPC.td as a result, to make it use the `PowerPC' class name
* Adjust Makefile accordingly

llvm-svn: 16174
 2004-09-05 02:42:44 +00:00
Misha Brukman
f55a7b3afa Renamed PPC32AsmPrinter.cpp => PowerPCAsmPrinter.cpp as the Darwin and AIX asm 
printers are now unified into one file.

llvm-svn: 16173
 2004-09-05 02:27:37 +00:00
Nate Begeman
56a134d07a Include MathExtras.h to fix build breakage, thanks to Vladimir 
llvm-svn: 16164
 2004-09-04 14:51:26 +00:00
Nate Begeman
e816600b3e All PPC instructions are now auto-printed 
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out

llvm-svn: 16163
 2004-09-04 05:00:00 +00:00
Nate Begeman
3bad485eec Convert remaining X-Form and Pseudo instructions over to asm writer 
llvm-svn: 16142
 2004-09-02 08:13:00 +00:00
Reid Spencer
c4abcbefb1 Changes For Bug 352 
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.

llvm-svn: 16137
 2004-09-01 22:55:40 +00:00
Nate Begeman
220175aa4d convert M and MD form instructions to generated asm writer 
llvm-svn: 16121
 2004-08-31 02:28:08 +00:00
Nate Begeman
e58512a61c Move yet more instructions over to being printed by the generated asm writer 
llvm-svn: 16112
 2004-08-30 02:28:06 +00:00
Nate Begeman
7792aa1f8b Convert A-Form instructions to auto-generated asm writer 
llvm-svn: 16107
 2004-08-29 22:45:13 +00:00
Nate Begeman
68e2dd66af Improvements to int->float cast code for PPC-64 
llvm-svn: 16105
 2004-08-29 22:02:43 +00:00
Nate Begeman
923af3763d Implement the following missing functionality in the PPC backend: 
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite.  Fixes Regression/casts

llvm-svn: 16081
 2004-08-29 08:19:32 +00:00
Nate Begeman
c0e42be976 Register sizes are in bits, not bytes 
llvm-svn: 16070
 2004-08-27 04:28:10 +00:00
Nate Begeman
0069f07741 Kill a majority of unnecessary sign extensions for byte loads 
llvm-svn: 15991
 2004-08-22 08:10:15 +00:00
Nate Begeman
72ec463dc7 Don't hard code the offset of the saved R31 in functions with frame pointers 
llvm-svn: 15990
 2004-08-22 08:09:17 +00:00
Nate Begeman
e6aace2ecb Back out branchless SetCC code. While it helped a lot in some cases, it 
hurt a lot in others.  Instead, improve branching version of SetCC and
Select instructions.  The old code will be in CVS should we ever need to
dig it up again.

llvm-svn: 15979
 2004-08-21 20:42:14 +00:00
Chris Lattner
15593f74c1 Switch from bytes to bits for alignment. 
Also, change GPRC for PPC32 to align on 32-bit boundary instead of 64-bit

llvm-svn: 15975
 2004-08-21 20:14:40 +00:00
Chris Lattner
db3e26f50a Reduce uses of getRegClass 
llvm-svn: 15968
 2004-08-21 19:51:17 +00:00
Chris Lattner
23a0219a11 Fix warning 
llvm-svn: 15964
 2004-08-21 19:11:03 +00:00
Nate Begeman
dd700ce5e4 Move XForm instructions over to the auto-generated asm writer 
llvm-svn: 15962
 2004-08-21 05:56:39 +00:00
Nate Begeman
6c4bd28dc1 remove some things from the todo list. 
llvm-svn: 15956
 2004-08-20 18:46:54 +00:00
Chris Lattner
cd2b92c36e Do not register ppc64 yet, as it breaks the SparcV9 backend 
llvm-svn: 15955
 2004-08-20 18:09:18 +00:00
Nate Begeman
2f68d05d47 Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file. 
llvm-svn: 15952
 2004-08-20 09:56:22 +00:00
Misha Brukman
8bfcf0d2e9 Fix opcodes being printed in caps (the more general fix may be `AsmWriter') 
llvm-svn: 15932
 2004-08-19 21:56:12 +00:00
Misha Brukman
1bdac3b68d Stack space for argument passing is 32 regardless of 32- vs. 64-bit arch. 
Thanks to Nate Begeman for pointing this out.

llvm-svn: 15930
 2004-08-19 21:51:19 +00:00
Misha Brukman
70f027b623 LR needs to be saved at 16-byte offset on a 64-bit arch 
llvm-svn: 15929
 2004-08-19 21:36:14 +00:00
Misha Brukman
2c3423694a On 64-bit PowerPC, pointers are 8 bytes, so parameter area offset is 48, not 24 
llvm-svn: 15928
 2004-08-19 21:34:05 +00:00
Misha Brukman
21df6f6757 This PHI has 4 additional operands, not 2. 
llvm-svn: 15926
 2004-08-19 21:00:12 +00:00
Misha Brukman
e438dc224e Use the appropriate 64-bit register description file. 
llvm-svn: 15922
 2004-08-19 19:36:57 +00:00
Misha Brukman
ffaa056155 Fix more remaining 32-bit vestiges of PowerPC 
llvm-svn: 15919
 2004-08-19 18:49:58 +00:00
Misha Brukman
409030d6b4 Fix another vestige of the 32-bit PowerPC backend. 
llvm-svn: 15918
 2004-08-19 16:50:30 +00:00
Misha Brukman
9ec6a58d15 Correct character prepended to global symbols ('.'), use Mangler consistently 
llvm-svn: 15917
 2004-08-19 16:33:56 +00:00