Nadav Rotem
051a0524a1
AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function.
...
llvm-svn: 171170
2012-12-27 22:47:16 +00:00
Craig Topper
179835e645
Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses.
...
llvm-svn: 171166
2012-12-27 18:51:50 +00:00
Chandler Carruth
e20bfe3a35
Add support to BasicBlocks for iterating backwards over the
...
instructions. This just exposes the already present reverse iterators of
the instruction ilist.
llvm-svn: 171159
2012-12-27 12:00:56 +00:00
Chandler Carruth
3f86485d73
Provide a common half-open interval map info implementation, and just
...
re-use that for SlotIndexes. This way other users who want half-open
semantics can share the implementation.
llvm-svn: 171158
2012-12-27 11:29:17 +00:00
Chandler Carruth
e396ef7f05
Make this parameter be named consistently with most other
...
getAnalysisUsage implementations.
llvm-svn: 171157
2012-12-27 11:17:15 +00:00
Sean Silva
ffbd8c6222
docs: Add FAQ about "storing to a virtual register".
...
This came up for the N+1'st time today in IRC.
llvm-svn: 171155
2012-12-27 10:23:04 +00:00
Sean Silva
32965d0b6e
docs: Move link to the new "external tutorials" area.
...
llvm-svn: 171154
2012-12-27 08:57:08 +00:00
Alexey Samsonov
b3bcf27f5a
[ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if it describes one of 'interesting' allocas. Assume that allocas can go through casts and phi-nodes before apperaring as llvm.lifetime arguments
...
llvm-svn: 171153
2012-12-27 08:50:58 +00:00
Nadav Rotem
fcfd42040b
DAGCombinerInformation: add a getter that exposes the dagcombine level.
...
llvm-svn: 171152
2012-12-27 08:44:35 +00:00
Alexey Samsonov
319ccd0fdb
Fix new[]/delete mismatch in FullDependence spotted by AddressSanitizer
...
llvm-svn: 171150
2012-12-27 08:40:37 +00:00
Nadav Rotem
017cc9b165
docs: Update the benchmark with updated perf numbers.
...
llvm-svn: 171149
2012-12-27 08:32:44 +00:00
Nadav Rotem
2f6e04c7be
On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
...
register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.
PR14657.
llvm-svn: 171148
2012-12-27 08:15:45 +00:00
Nadav Rotem
76034b9bb4
AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook.
...
The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.
llvm-svn: 171146
2012-12-27 07:45:10 +00:00
Craig Topper
f3cf4daada
Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.
...
llvm-svn: 171143
2012-12-27 07:16:08 +00:00
Nadav Rotem
55c5987673
Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum.
...
Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase.
llvm-svn: 171142
2012-12-27 06:47:41 +00:00
Craig Topper
a44c63c7b9
Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.
...
llvm-svn: 171141
2012-12-27 06:34:54 +00:00
Craig Topper
56ee68554d
Update tablegen parser to allow defm names to start with #NAME.
...
llvm-svn: 171140
2012-12-27 06:32:52 +00:00
Craig Topper
10e18bc2f3
Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation.
...
llvm-svn: 171137
2012-12-27 03:35:44 +00:00
Craig Topper
8411715f87
Mark the divide instructions as hasSideEffects=0.
...
llvm-svn: 171136
2012-12-27 03:01:18 +00:00
Eric Christopher
7096eb5a5c
For the dwarf5 split debug info code split out the string section
...
per compile unit/skeleton compile unit. Update tests accordingly.
llvm-svn: 171133
2012-12-27 02:14:01 +00:00
Eric Christopher
eb6482f385
FileCheck-ize.
...
llvm-svn: 171132
2012-12-27 02:13:58 +00:00
Eric Christopher
4786ae2a5f
FileCheck-ize.
...
llvm-svn: 171131
2012-12-27 02:13:55 +00:00
Craig Topper
4c075a815b
Add hasSideEffects=0 to CMP*rr_REV.
...
llvm-svn: 171130
2012-12-27 02:08:46 +00:00
Nadav Rotem
798533821a
whitespace
...
llvm-svn: 171129
2012-12-27 02:04:12 +00:00
Craig Topper
5650ea25b7
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.
...
llvm-svn: 171128
2012-12-27 02:01:33 +00:00
Eric Christopher
c6fa1e95a2
Right now all of the relocations are 32-bit dwarf, and the relocation
...
information doesn't return an addend for Rel relocations. Go ahead
and use this information to fix relocation handling inside dwarfdump
for 32-bit ELF REL.
llvm-svn: 171126
2012-12-27 01:07:07 +00:00
Nadav Rotem
4cad811734
If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified.
...
PR14719.
llvm-svn: 171124
2012-12-26 23:30:53 +00:00
Craig Topper
9e3cb122f1
Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem.
...
llvm-svn: 171123
2012-12-26 23:27:57 +00:00
Craig Topper
fe4506dc6c
Add hasSideEffects=0 to some atomic instructions.
...
llvm-svn: 171122
2012-12-26 23:08:12 +00:00
Craig Topper
c4205e1d63
Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects.
...
llvm-svn: 171121
2012-12-26 22:19:23 +00:00
Nick Lewycky
7f19cf03a6
80 columns. No functionality change.
...
llvm-svn: 171120
2012-12-26 22:00:49 +00:00
Nick Lewycky
3aba2e21ea
Remove mid-optimizer warning. This situation should be handled differently,
...
such as by a compiler warning, a check in clang -fsanitizer=undefined, being
optimized to unreachable, or a combination of the above. PR14722.
llvm-svn: 171119
2012-12-26 22:00:35 +00:00
Craig Topper
152bee45fa
Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier.
...
llvm-svn: 171118
2012-12-26 21:30:22 +00:00
Craig Topper
2b01799bba
Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.
...
llvm-svn: 171117
2012-12-26 21:04:30 +00:00
Nadav Rotem
758e442bb6
Update the docs with the new workload that was added.
...
llvm-svn: 171115
2012-12-26 19:45:00 +00:00
Nadav Rotem
90712b89cc
LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1
...
llvm-svn: 171114
2012-12-26 19:08:17 +00:00
Eli Bendersky
38abc56548
Fix comment typo
...
llvm-svn: 171113
2012-12-26 18:15:42 +00:00
Evgeniy Stepanov
3c52fb6e43
[msan] Raise alignment of origin stores/loads when possible.
...
Origin alignment is as high as the alignment of the corresponding application
location, but never less than 4.
llvm-svn: 171110
2012-12-26 11:55:09 +00:00
Evgeniy Stepanov
e64939756e
[msan] Expand the file comment with track-origins info.
...
llvm-svn: 171109
2012-12-26 10:59:00 +00:00
Benjamin Kramer
6f560e4b24
Fix quoting in configure. Patch by Krzysztof Parzyszek!
...
llvm-svn: 171108
2012-12-26 10:48:49 +00:00
Craig Topper
d3212f7ab5
Merge still more SSE/AVX instruction definitions.
...
llvm-svn: 171103
2012-12-26 07:54:43 +00:00
Craig Topper
e1a7e48937
Merge more SSE/AVX instruction definitions.
...
llvm-svn: 171102
2012-12-26 07:20:35 +00:00
NAKAMURA Takumi
5b4a443c29
TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction().
...
Reported by Yang Yongyong, thanks!
llvm-svn: 171101
2012-12-26 06:43:14 +00:00
Nadav Rotem
034faa077d
revert an accidental commit.
...
llvm-svn: 171098
2012-12-26 06:16:03 +00:00
Craig Topper
e11b743aa8
Fix 80 column violation.
...
llvm-svn: 171097
2012-12-26 06:15:53 +00:00
Craig Topper
6bb87eb1c5
Fix class name in comment.
...
llvm-svn: 171096
2012-12-26 06:15:09 +00:00
Craig Topper
6548cfbc58
Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.
...
llvm-svn: 171095
2012-12-26 06:14:15 +00:00
Nadav Rotem
fec894619f
Doc: add fmuladd to the list of vectorizeable functions. Thanks hfinkel.
...
llvm-svn: 171094
2012-12-26 06:03:35 +00:00
Craig Topper
891ef3c0d5
Remove 'v' from mnemonic to fix asm matching failures.
...
llvm-svn: 171093
2012-12-26 06:02:15 +00:00
Craig Topper
0466a426a3
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions.
...
llvm-svn: 171092
2012-12-26 05:49:15 +00:00