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Author SHA1 Message Date
Andrew Trick
05d7cb17d5 LSR: Reuse the post-inc expansion of expressions. 
This avoids unnecessary expansion of expressions and allows the SCEV
expander to work on expression DAGs, not just trees.
Fixes PR11090.

llvm-svn: 141870
 2011-10-13 17:31:47 +00:00
Daniel Dunbar
86b464dff5 build: Remove some stray LLVMC configure variables. 
llvm-svn: 141869
 2011-10-13 17:27:34 +00:00
Andrew Trick
38d4b87695 SCEV: Rewrite TrandformForPostIncUse to handle expression DAGs, not 
just expression trees.

Partially fixes PR11090. Test case will be with the full fix.

llvm-svn: 141868
 2011-10-13 17:21:09 +00:00
Andrew Trick
5286636188 Slightly more useful tracing. 
llvm-svn: 141867
 2011-10-13 17:06:38 +00:00
Benjamin Kramer
a705595096 Force CPU type on test so it doesn't accidentally emit movbe instead of bswap on Intel Atom CPUs. 
llvm-svn: 141863
 2011-10-13 14:27:54 +00:00
Kalle Raiskila
15993a5d28 Mark 'branch indirect' instruction as an indirect branch. 
Not having it confused assembly printing of jumptables.

llvm-svn: 141862
 2011-10-13 11:40:03 +00:00
Bill Wendling
dcd9c25744 More closely follow libgcc, which has code after the `ret' instruction to 
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.

llvm-svn: 141859
 2011-10-13 08:24:19 +00:00
Bill Wendling
2a571af745 Revert r141854 because it was causing failures: 
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857
 2011-10-13 07:48:07 +00:00
Bill Wendling
a6bf25f30a Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I. 
llvm-svn: 141856
 2011-10-13 07:42:32 +00:00
Cameron Zwarich
fcbdff2af3 Use an existing method. 
llvm-svn: 141855
 2011-10-13 07:36:41 +00:00
Craig Topper
eb29e18c9b Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141854
 2011-10-13 07:09:14 +00:00
Craig Topper
0d25fa802f Add 'implicit EFLAGS' to patterns for popcnt and lzcnt 
llvm-svn: 141853
 2011-10-13 06:18:52 +00:00
Nick Lewycky
70cfa65b6b Elf_Word is not POD! Stop using it in a DenseMap. 
llvm-svn: 141851
 2011-10-13 03:30:21 +00:00
Nick Lewycky
714cb9cf31 If MI is deleted then remove it from the set. If a new MI is created, it could 
have the same address as the one we deleted, and we don't want that in the set
yet. Noticed by inspection.

llvm-svn: 141849
 2011-10-13 02:16:18 +00:00
Nick Lewycky
f4037f6420 Tabs to spaces. 
llvm-svn: 141844
 2011-10-13 01:09:50 +00:00
Nick Lewycky
157477efa7 Add missing braces to pacify GCC's -Wparentheses. 
llvm-svn: 141842
 2011-10-13 00:54:59 +00:00
Michael J. Spencer
162052e2b2 Add missing ELF constants. 
llvm-svn: 141840
 2011-10-13 00:16:25 +00:00
Jakob Stoklund Olesen
f38db50fed Also inflate register classes around inline asm. 
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.

This fixes PR11078.

llvm-svn: 141836
 2011-10-12 23:37:40 +00:00
Jakob Stoklund Olesen
9349890ed8 Add MachineInstr::getRegClassConstraint(). 
Most instructions have some requirements for their register operands.
Usually, this is expressed as register class constraints in the
MCInstrDesc, but for inline assembly the constraints are encoded in the
flag words.

llvm-svn: 141835
 2011-10-12 23:37:36 +00:00
Jakob Stoklund Olesen
d406c95461 Extract a method for finding the inline asm flag operand. 
llvm-svn: 141834
 2011-10-12 23:37:33 +00:00
Jakob Stoklund Olesen
3d62f52b22 Encode register class constreaints in inline asm instructions. 
The inline asm operand constraint is initially encoded in the virtual
register for the operand, but that register class may change during
coalescing, and the original constraint is lost.

Encode the original register class as part of the flag word for each
inline asm operand.  This makes it possible to recover the actual
constraint required by inline asm, just like we can for normal
instructions.

llvm-svn: 141833
 2011-10-12 23:37:29 +00:00
Eli Friedman
b70efeb6fc Attempt to fix MSVC build. 
llvm-svn: 141831
 2011-10-12 23:14:41 +00:00
Bill Wendling
60bfb5d707 We need to verify that the machine instruction we're using as a replacement for 
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>

llvm-svn: 141830
 2011-10-12 23:03:40 +00:00
Eli Friedman
f6209d7abe Use a utility from MathExtras to clarify a check and avoid undefined behavior. Based on patch by Ahmed Charles. 
llvm-svn: 141829
 2011-10-12 22:46:45 +00:00
Owen Anderson
a3ffb86b9a The VMAs stored in the symbol table of a MachO file are absolute addresses, not offsets from the section. 
llvm-svn: 141828
 2011-10-12 22:37:10 +00:00
Eli Friedman
400fe75ba1 Use unsigned multiply to hash integers, so we don't end up with undefined behavior for large signed integers. Based on patch by Ahmed Charles. 
llvm-svn: 141827
 2011-10-12 22:25:45 +00:00
Lang Hames
069669eb13 Removed colons from some target datalayout strings in test, since they don't match the required format. 
llvm-svn: 141825
 2011-10-12 22:24:17 +00:00
Owen Anderson
6931df0d99 Don't label a STAB debugging symbol as a function symbol. 
llvm-svn: 141824
 2011-10-12 22:23:12 +00:00
Owen Anderson
6e41e4318d sectionContainsSymbol needs to be based on VMA's rather than section indices to properly account for files with segment load commands that contain no sections. 
llvm-svn: 141822
 2011-10-12 22:21:32 +00:00
Eli Friedman
22c39edd2e Fix a couple hash functions so that they do not depend on undefined shifts. Based on patch by Ahmed Charles. 
llvm-svn: 141820
 2011-10-12 22:00:26 +00:00
Jim Grosbach
b9dddb0d13 ARM addrmode5 represents the 'U' bit of the encoding backwards. 
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.

llvm-svn: 141819
 2011-10-12 21:59:02 +00:00
Eli Friedman
d9ebbc6cf5 Fix APFloat::getSmallestNormalized so the shift doesn't depend on undefined behavior. Patch from Ahmed Charles. 
llvm-svn: 141818
 2011-10-12 21:56:19 +00:00
Eli Friedman
cda27f4c18 Fix APFloat::getLargest so that it actually returns the correct value. Found by accident while reviewing a patch to nearby code. 
llvm-svn: 141816
 2011-10-12 21:51:36 +00:00
Owen Anderson
43ef26d840 Section indices in MachO symbol tables begin at 1, not 0. 
llvm-svn: 141815
 2011-10-12 21:43:24 +00:00
Kevin Enderby
974c799a5a Finish supporting cpp #file/line comments in assembler for error messages. So 
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895

llvm-svn: 141814
 2011-10-12 21:38:39 +00:00
Evan Cheng
6ffc02582e Disable machine LICM speculation check (for profitability) until I have time to investigate the regressions. 
llvm-svn: 141813
 2011-10-12 21:33:49 +00:00
Cameron Zwarich
19d2ebc9a4 To find the exiting VN of a LiveInterval from a block, use the previous slot 
rather than the previous index. If a block has a single instruction, the
previous index may be in a different basic block.

I have no clue how this used to work on all of test-suite, because now this
failure is seen quite often when trying to compile code with -strong-phi-elim.
This fixes PR10252.

llvm-svn: 141812
 2011-10-12 21:24:54 +00:00
Jim Grosbach
422576b6e8 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00
Nick Lewycky
add3022a37 Hoist vector.size() computation out of the loop. No functionality change. 
llvm-svn: 141807
 2011-10-12 20:20:48 +00:00
Jim Grosbach
71dbc175ce addrmode2 is gone from these, so no need for the reg0 operand. 
llvm-svn: 141794
 2011-10-12 18:11:24 +00:00
Jim Grosbach
2a501996ab ARM encoding tests for STC. 
llvm-svn: 141787
 2011-10-12 17:36:13 +00:00
Jim Grosbach
eb7acc978a ARM parsing and encoding for the <option> form of LDC/STC instructions. 
llvm-svn: 141786
 2011-10-12 17:34:41 +00:00
Jim Grosbach
70a91e2da7 80 columns. 
llvm-svn: 141781
 2011-10-12 16:36:01 +00:00
Jim Grosbach
3b205dab2d Tidy up. Formatting. 
llvm-svn: 141780
 2011-10-12 16:34:37 +00:00
Dan Gohman
5acb47274d Fix a thinko that Nick noticed. The previous code actually worked as 
intended, but only by accident.

llvm-svn: 141779
 2011-10-12 15:56:56 +00:00
NAKAMURA Takumi
35b6744077 lib/Object/ELFObjectFile.cpp: Fix undefined behavior for MC/ELF/many-section.s not to fail (on msvc). 
DenseMap::lookup(k) would return "default constructor value" when k was not met. It would be useless when value type were POD.

llvm-svn: 141774
 2011-10-12 10:28:55 +00:00
Bill Wendling
bec4f3b9f3 Expand the check for a landing pad so that it looks at the basic block's 
containing loop's header to see if that's a landing pad. If it is, then we don't
want to hoist instructions out of the loop and above the header.

llvm-svn: 141767
 2011-10-12 02:58:01 +00:00
Jakob Stoklund Olesen
0f662145ef Use an existing function. 
llvm-svn: 141763
 2011-10-12 01:24:51 +00:00
Akira Hatanaka
68c6bb2c02 Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. 
llvm-svn: 141761
 2011-10-12 01:05:13 +00:00
Akira Hatanaka
08230e45e0 Fix encoding of 32-bit integer instructions. Change names of operands and nodes. 
Remove unused classes.

llvm-svn: 141757
 2011-10-12 00:56:06 +00:00