1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
Commit Graph

174539 Commits

Author SHA1 Message Date
Richard Trieu
6d6fc335ec Add namespace to some types.
llvm-svn: 352725
2019-01-31 04:33:11 +00:00
Matt Arsenault
a2306ee5f1 Fix missing C++ mode comment in header
llvm-svn: 352724
2019-01-31 04:27:17 +00:00
David L. Jones
f56c7f0762 Revert "Reapply "[CGP] Check for existing inttotpr before creating new one""
This change reverts r351626.

The changes in r351626 cause quadratic work in several cases. (See r351626 thread on llvm-commits for details.)

llvm-svn: 352722
2019-01-31 03:28:46 +00:00
Matt Arsenault
d57348e6c2 GlobalISel: Handle odd splits in fewerElementsVector for load/store
llvm-svn: 352720
2019-01-31 02:46:05 +00:00
Matt Arsenault
1f33c5710d GlobalISel: Implement narrowScalar for bswap
llvm-svn: 352719
2019-01-31 02:34:03 +00:00
Matt Arsenault
dd59d17aab GlobalISel: Don't call changingInstruction before giving up
llvm-svn: 352718
2019-01-31 02:22:39 +00:00
Matt Arsenault
51c3d3146e GlobalISel: Allow bitcount ops to have different result type
For AMDGPU the result is always 32-bit for 64-bit inputs.

llvm-svn: 352717
2019-01-31 02:09:57 +00:00
Matt Arsenault
31558bae75 GlobalISel: Use helper function for MMO splitting
Also fix an alignment bug getMachineMemOperand. If the
tracked value is null, the offset isn't tracked so the
base alignment needs to be reduced.

llvm-svn: 352716
2019-01-31 01:49:58 +00:00
Kostya Serebryany
e52e1e1e30 [libFuzzer] update docs
llvm-svn: 352715
2019-01-31 01:47:29 +00:00
Evandro Menezes
d240a1f88f [InstCombine] Expand testing for Windows (NFC)
Added the checks to the existing cases when the target is Win64.

llvm-svn: 352714
2019-01-31 01:41:39 +00:00
Matt Arsenault
1067bf29d3 GlobalISel: Fix creating MMOs with align 0
llvm-svn: 352712
2019-01-31 01:38:47 +00:00
Craig Topper
2cdf09b4b5 [X86] Add a 32-bit command line to avx512-intrinsics.ll. Move all 64-bit mode only intrinsics to avx512-intrinsics-x86_64.ll.
Most of the other intrinsic tests have a 32-bit command lines.

llvm-svn: 352708
2019-01-31 00:49:40 +00:00
Evandro Menezes
7d41565964 [InstCombine] Simplify check clauses in test (NFC)
llvm-svn: 352707
2019-01-31 00:49:27 +00:00
Peter Collingbourne
b68b5c4a29 Reland "gn build: Add BPF target."
Differential Revision: https://reviews.llvm.org/D57436

llvm-svn: 352705
2019-01-31 00:42:02 +00:00
Nico Weber
1335b1046c lit: Let lit.util.which() return a normcase()ed path
LLVMConfig.with_environment() uses os.path.normcase(os.path.normpath(x)) to
normalize temporary env vars. LLVMConfig.use_clang() uses with_environment() to
temporarily set PATH and then look for clang there. This means that on Windows,
clang will be run with a path like c:\foo\bin\clang.EXE (with a lower-case
"C:").

lit.util.which() used to not do this, which means the executables added in
clang/test/lit.cfg.py (e.g. c-index-test) were run with a path like
C:\foo\bin\c-index-test.EXE (because both CMake and GN happen to write
clang_tools_dir with an upper-case C to lit.site.cfg.py).

clang/test/Index/pch-from-libclang.c requires that both c-index-test and clang
use _exactly_ the same resource dir path (same case and everything), because a
hash of the resource directory is used as module cache path.

This patch is necessary but not sufficient to make pch-from-libclang.c pass on
Windows.

Differential Revision: https://reviews.llvm.org/D57343

llvm-svn: 352704
2019-01-31 00:40:43 +00:00
Thomas Lively
7fe75e768c [LegalizeVectorTypes] Allow illegal indices when splitting extract_vector_elt
Summary:
Fixes PR40267, in which the removed assertion was triggering on
perfectly valid IR. As far as I can tell, constant out of bounds
indices should be allowed when splitting extract_vector_elt, since
they will simply be propagated as out of bounds indices in the
resulting split vector and handled appropriately elsewhere.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya

Differential Revision: https://reviews.llvm.org/D57471

llvm-svn: 352702
2019-01-31 00:35:37 +00:00
Craig Topper
1c7eed7778 [LegalizeTypes] Use report_fatal_error instead of llvm_unreachable in the default case of some type legalization handlers that can be reached with intrinsics with result or operands that aren't legal types.
These can be triggered by mistakenly using a 64-bit mode only intrinsics with a -mtriple=i686. Using report_fatal_error gives a better experience for this mistake in release builds instead of probably crashing.

We already do this for some of the vector type legalization handles.

llvm-svn: 352699
2019-01-31 00:04:48 +00:00
Craig Topper
74077920f5 [X86] Remove handling of ISD::INTRINSIC_WO_CHAIN in ReplaceNodeResults.
I believe this was there to handle avx512bw intrinsics that returned i64 type in 32-bit mode. But all those intrinsics have since been changed to v64i1 results or replaced with generic IR.

llvm-svn: 352698
2019-01-31 00:04:46 +00:00
Craig Topper
818846eaba [X86] Add test case for pr40539. NFC
llvm-svn: 352697
2019-01-31 00:04:42 +00:00
Heejin Ahn
845f861c09 [WebAssembly] Remove TODO on wasm.extract.exception intrinsic (NFC)
Summary:
We planned to delete this intrinsic and do custom lowering from
`wasm.get.exception`, which has a token argument, to
`EXTRACT_EXCEPTION`, a wasm pseudo instruction that simulates popping a
value from the wasm stack.

To do that, we need to introduce a new `WebAssemblyISD` node for this,
which itself is not a problem, but also have to introduce the
`WebAssemblyISD` namespace in SelectionDAGBuilder.cpp. I don't think any
other targets are doing that in the file. And also putting a
target-specific intrinsic in the common file is a little weird too. (All
other intrinsic functions in this `visitIntrinsicCall` functions are not
target-specific ones. Other target-specific intrinsics are usually
handled in `lib/Target/[TargetName]/[TargetName]ISelLowering.cpp`. The
reason we can't do this is it has a token argument.

Anyway, so I think I prefer the current code with one redundant
intrinsic more than adding one more `WebAssemblyISD` node and
also introducing the `WebAssemblyISD` namespace into
SelectionDAGBuilder.cpp. What do you think?

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D57480

llvm-svn: 352695
2019-01-30 23:53:36 +00:00
Zachary Turner
da607f74a1 [RuntimeDyld] Don't try to allocate sections with align 0.
ELF sections allow 0 for the alignment, which is specified to
be the same as 1.  However many clients do not expect this and
will behave poorly in the presence of a 0-aligned section (for
example by trying to modulo something by the section alignment).
We can be more polite by making sure that we always pass a
non-zero value to clients.

Differential Revision: https://reviews.llvm.org/D57482

llvm-svn: 352694
2019-01-30 23:52:32 +00:00
Jessica Paquette
156cec86e5 [GlobalISel][AArch64] Select G_FEXP
This teaches the legalizer to handle G_FEXP in AArch64. As a result, it also
allows us to select G_FEXP.

It...

- Updates the legalizer-info tests
- Adds a test for legalizing exp
- Updates the existing fp tests to show that we can now select G_FEXP

https://reviews.llvm.org/D57483

llvm-svn: 352692
2019-01-30 23:46:15 +00:00
Amara Emerson
4ff1612c12 [GlobalISel][LegalizerHelper] Add some missing MI change observer calls.
No test as it's a preventative fix.

llvm-svn: 352691
2019-01-30 23:42:46 +00:00
Chen Zheng
238fb80db4 [PowerPC] delete no more needed workaround for readsRegister() in PowerPC
Differential Revision: https://reviews.llvm.org/D57439

llvm-svn: 352689
2019-01-30 23:18:38 +00:00
Matt Arsenault
5fedb6baff MIR: Reject non-power-of-4 alignments in MMO parsing
llvm-svn: 352686
2019-01-30 23:09:28 +00:00
Jessica Paquette
d46e179ece [GlobalISel][AArch64] Select G_FABS
This adds instruction selection support for G_FABS in AArch64. It also updates
the existing basic FP tests, adds a selection test for G_FABS.

https://reviews.llvm.org/D57418

llvm-svn: 352684
2019-01-30 22:54:21 +00:00
Sam Clegg
a491f1eb8e [WebAssembly] MC: Use WritePatchableLEB helper function. NFC.
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D57477

llvm-svn: 352683
2019-01-30 22:47:35 +00:00
Heejin Ahn
39b0555c03 [WebAssembly] Restore stack pointer right after catch instruction
Summary:
After the staack is unwound due to a thrown exxception,
`__stack_pointer` global can point to an invalid address. So
a `global.set` to restore `__stack_pointer` should be inserted right
after `catch` instruction.

But after r352598 the `global.set` instruction is inserted not right
after `catch` but after `block` - `br-on-exn` - `end_block` -
`extract_exception` sequence. This CL fixes it.

While doing that, we can actually move ReplacePhysRegs pass after
LateEHPrepare and merge EHRestoreStackPointer pass into LateEHPrepare,
and now placing `global.set` to `__stack_pointer` right after `catch` is
much easier. Otherwise it is hard to guarantee that `global.set` is
still right after `catch` and not touched with other transformations, in
which case we have to do something to hoist it.

Reviewers: dschuff

Subscribers: mgorny, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D57421

llvm-svn: 352681
2019-01-30 22:44:45 +00:00
Sanjay Patel
31c3bd6557 [DAGCombiner] sub X, 0/1 --> add X, 0/-1
This extends the existing transform for:
add X, 0/1 --> sub X, 0/-1
...to allow the sibling subtraction fold.

This pattern could regress with the proposed change in D57401.

llvm-svn: 352680
2019-01-30 22:41:35 +00:00
Sanjay Patel
3276e2f2d5 [AArch64][x86] add tests for add/sub signbits fold; NFC
As discussed/shown in D57401, we are missing a fold for
subtract of 0/1 --> add 0/-1.

llvm-svn: 352678
2019-01-30 21:58:20 +00:00
Jessica Paquette
d5349f419b [GlobalISel][AArch64] Add instruction selection support for @llvm.log2
This teaches GlobalISel to emit a RTLib call for @llvm.log2 when it encounters
it.

It updates the existing floating point tests to show that we don't fall back on
the intrinsic, and select the correct instructions. It also adds a legalizer
test for G_FLOG2.

https://reviews.llvm.org/D57357

llvm-svn: 352673
2019-01-30 21:16:04 +00:00
Jessica Paquette
d03d1c2ace [GlobalISel][AArch64] Add instruction selection support for @llvm.sqrt
This teaches the legalizer about G_FSQRT in AArch64. Also adds a legalizer
test for G_FSQRT, a selection test for it, and updates existing floating point
tests.

https://reviews.llvm.org/D57361

llvm-svn: 352671
2019-01-30 21:03:52 +00:00
Jessica Paquette
5e71e4e829 [GlobalISel] Add IRTranslator support for @llvm.sqrt -> G_FSQRT
Follow-up commit to https://reviews.llvm.org/D57359. (r352668)

This adds IRTranslator support for recognising a @llvm.sqrt intrinsic and
translating it into a G_FSQRT.

https://reviews.llvm.org/D57360

llvm-svn: 352670
2019-01-30 20:58:14 +00:00
Jessica Paquette
2b66bd8551 [GlobalISel] Introduce a G_FSQRT generic instruction
This introduces a generic instruction for computing the floating point
square root of a value.

Right now, we can't select @llvm.sqrt, so this is working towards fixing that.

llvm-svn: 352668
2019-01-30 20:49:50 +00:00
Wolfgang Pieb
f92e9f9f5a Reverting r352642 - Handle restore instructions in LiveDebugValues - as it's causing
assertions on some buildbots.

llvm-svn: 352666
2019-01-30 20:37:14 +00:00
Erik Pilkington
133b958621 Add a 'dynamic' parameter to the objectsize intrinsic
This is meant to be used with clang's __builtin_dynamic_object_size.
When 'true' is passed to this parameter, the intrinsic has the
potential to be folded into instructions that will be evaluated
at run time. When 'false', the objectsize intrinsic behaviour is
unchanged.

rdar://32212419

Differential revision: https://reviews.llvm.org/D56761

llvm-svn: 352664
2019-01-30 20:34:35 +00:00
Philip Reames
bee4e4e275 [Tests] Add tests for propagation of undef elements in vector GEPs
llvm-svn: 352662
2019-01-30 20:06:24 +00:00
Craig Topper
18b9e8a676 [X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7.
This fixes the test case in PR35982 by preventing MMX instructions that read MM0-7 from being moved below EMMS/FEMMS by the post RA scheduler.

Though as discussed in bugzilla, this is not a complete fix. There is still the possibility of reordering in IR or by the pre-RA scheduler.

Differential Revision: https://reviews.llvm.org/D57298

llvm-svn: 352660
2019-01-30 19:57:01 +00:00
Nico Weber
d0c7f7c148 gn build: Set executable bit on get.py
llvm-svn: 352659
2019-01-30 19:53:58 +00:00
Philip Reames
b308fb024d SimplifyDemandedVectorElts for all intrinsics
The point is that this simplifies integration of new intrinsics into SimplifiedDemandedVectorElts, and ensures we don't miss any existing ones.

This is intended to be NFC-ish, but as seen from the diffs, can produce slightly different output.  This is due to order of transforms w/in instcombine resulting in two slightly different fixed points.  That's something we should fix, but isn't a problem w/this patch per se.

Differential Revision: https://reviews.llvm.org/D57398

llvm-svn: 352653
2019-01-30 19:21:11 +00:00
Wolfgang Pieb
422de19033 The test comitted with r348896 needed -march=x86=64 on the llc command line.
llvm-svn: 352651
2019-01-30 19:15:43 +00:00
Yonghong Song
763dfa2757 Revert "gn build: Add BPF target."
This reverts commit r352638.

The change in this patch is not trivial and it is merged
without component owner approval.

llvm-svn: 352649
2019-01-30 19:13:16 +00:00
Wolfgang Pieb
25357489cd [DEBUGINFO] Handle restore instructions in LiveDebugValues
The LiveDebugValues pass recognizes spills but not restores, which can 
cause large gaps in location information for some variables, depending
on control flow. This patch make LiveDebugValues recognize restores and
generate appropriate DBG_VALUE instructions. 

Reviewers: aprantl, NicolaPrica

Differential Revision: https://reviews.llvm.org/D57271

llvm-svn: 352642
2019-01-30 18:34:07 +00:00
Jordan Rupprecht
50335129ab [llvm-objcopy][NFC] More error propagation (linkToBuildIdDir)
llvm-svn: 352640
2019-01-30 18:13:30 +00:00
Peter Collingbourne
6ea44aa869 gn build: Add BPF target.
Differential Revision: https://reviews.llvm.org/D57436

llvm-svn: 352638
2019-01-30 18:04:08 +00:00
Matt Arsenault
2868917308 GlobalISel: Add simpler way of always specifying custom lowering
llvm-svn: 352637
2019-01-30 17:52:25 +00:00
Matt Arsenault
acfdd5ea72 GlobalISel: Add assert that legalize mutation makes sense
I've repeatedly encountered bugs resulting from custom legalize
mutations returning nonsense legalize results, such as increasing the
number of elements for FewerElements. Add an assert function to make
sure the type to mutate to is consistent with the legalize action.

llvm-svn: 352636
2019-01-30 17:52:23 +00:00
Matt Arsenault
a49701a9f1 AMDGPU: Stop generating unused intrinsic .inc files
llvm-svn: 352635
2019-01-30 17:25:37 +00:00
Simon Pilgrim
e4faf9f948 [X86][AVX] Prefer to combine shuffle to broadcasts whenever possible
This is the first step towards improving broadcast support on AVX1 targets.

llvm-svn: 352634
2019-01-30 16:19:19 +00:00
Simon Pilgrim
15e0e2038a [utils] Fix update scripts output when run on python3.
This fixes a "bytes-like object is required, not 'str'" python3 error I hit on update_llc_test_checks.py (but present on the other scripts as well) by matching what update_mca_test_checks.py already does, plus I've added an explicit 'utf-8' encoding.

llvm-svn: 352633
2019-01-30 16:15:59 +00:00