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071b4ec891
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1791 Commits

Author SHA1 Message Date
Jim Grosbach
071b4ec891 To get more thorough testing from llc-beta nightly runs, do dynamic stack 
realignment regardless of whether it's strictly necessary.

llvm-svn: 85476
 2009-10-29 02:41:21 +00:00
Bob Wilson
fc1194919b Revert r85346 change to control tail merging by CodeGenOpt::Level. 
I'm going to redo this using the OptimizeForSize function attribute.

llvm-svn: 85426
 2009-10-28 20:46:46 +00:00
Bob Wilson
af37728221 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411
 2009-10-28 18:26:41 +00:00
Evan Cheng
519b231883 fconsts and fconstd are obviously re-materializable. 
llvm-svn: 85410
 2009-10-28 18:19:56 +00:00
Jim Grosbach
e42dc83a9f Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2. 
llvm-svn: 85406
 2009-10-28 17:33:28 +00:00
Evan Cheng
16ed5ac7ff Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. 
llvm-svn: 85381
 2009-10-28 06:55:03 +00:00
Evan Cheng
1babe43881 Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Bob Wilson
b709aa6b3c Add an indirect branch pattern for ARM. Testcase will be coming soon. 
llvm-svn: 85355
 2009-10-28 00:37:03 +00:00
Bob Wilson
98c9fb94ab Record CodeGen optimization level in the BranchFolding pass so that we can 
use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346
 2009-10-27 23:49:38 +00:00
Jim Grosbach
7c0566a5cc Enable virtual register based frame index scavenging by default for ARM & T2. 
llvm-svn: 85335
 2009-10-27 22:52:29 +00:00
Jim Grosbach
a6946f0f50 Infrastructure for dynamic stack realignment on ARM. For now, this is off by 
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.

llvm-svn: 85333
 2009-10-27 22:45:39 +00:00
Johnny Chen
b746e248cd Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
llvm-svn: 85299
 2009-10-27 20:51:49 +00:00
Johnny Chen
d63b06e0f6 Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.

llvm-svn: 85297
 2009-10-27 20:45:15 +00:00
Bob Wilson
5ca76e601f Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.

llvm-svn: 85280
 2009-10-27 19:52:03 +00:00
Johnny Chen
528c66b30c Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271
 2009-10-27 18:44:24 +00:00
Johnny Chen
37851c95e8 Test commit. Added '.' to the comment line. 
llvm-svn: 85255
 2009-10-27 17:25:15 +00:00
Rafael Espindola
7eb2a8fb0b Correctly align double arguments in the stack. 
llvm-svn: 85235
 2009-10-27 14:09:44 +00:00
Evan Cheng
032eef9720 Now VFP instructions. 
llvm-svn: 85186
 2009-10-27 00:20:49 +00:00
Evan Cheng
f30e5556ba Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85184
 2009-10-27 00:08:59 +00:00
Evan Cheng
a883c2ebb7 Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85178
 2009-10-26 23:45:59 +00:00
Bob Wilson
5a870f848e Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173
 2009-10-26 22:59:12 +00:00
Bob Wilson
ace97183c7 Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.

llvm-svn: 85169
 2009-10-26 22:42:13 +00:00
Bob Wilson
32ee4ee163 Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.

llvm-svn: 85167
 2009-10-26 22:34:44 +00:00
David Goodwin
f6199e95b0 Break anti-dependence breaking out into its own class. 
llvm-svn: 85127
 2009-10-26 16:59:04 +00:00
Jim Grosbach
eae0e509c0 of -> or 
llvm-svn: 85065
 2009-10-25 19:14:48 +00:00
Jim Grosbach
29b842a6c1 80-column cleanup 
llvm-svn: 85064
 2009-10-25 18:55:46 +00:00
Evan Cheng
d748ce45ab Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. 
llvm-svn: 85049
 2009-10-25 07:53:28 +00:00
Evan Cheng
77ecc0adc5 Don't forget subreg indices when folding load / store. 
llvm-svn: 85048
 2009-10-25 07:52:27 +00:00
Nick Lewycky
2b8400628d Remove includes of Support/Compiler.h that are no longer needed after the 
VISIBILITY_HIDDEN removal.

llvm-svn: 85043
 2009-10-25 06:57:41 +00:00
Nick Lewycky
711c726c97 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
 2009-10-25 06:33:48 +00:00
Evan Cheng
0e5c6b3b69 80 col violation. 
llvm-svn: 84986
 2009-10-24 02:07:42 +00:00
Jim Grosbach
e295e49760 Restrict Thumb1 register allocation to low registers, even for instructions that 
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.

llvm-svn: 84982
 2009-10-24 00:19:24 +00:00
Jim Grosbach
5b5a404677 FIXME no longer applies. R12 and R3 are available for allocation 
llvm-svn: 84977
 2009-10-23 23:07:42 +00:00
David Goodwin
82c1dd9754 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
llvm-svn: 84911
 2009-10-22 23:19:17 +00:00
Bob Wilson
8f4f73da55 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
llvm-svn: 84868
 2009-10-22 16:52:21 +00:00
Evan Cheng
2edd1efa46 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
llvm-svn: 84843
 2009-10-22 06:48:32 +00:00
Evan Cheng
d411ac1267 Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. 
llvm-svn: 84842
 2009-10-22 06:47:35 +00:00
Evan Cheng
0c6aa52214 Trim more includes. 
llvm-svn: 84832
 2009-10-22 05:11:00 +00:00
Evan Cheng
166f455456 Trim include. 
llvm-svn: 84831
 2009-10-22 05:08:49 +00:00
Evan Cheng
8fdd1661fa Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
llvm-svn: 84813
 2009-10-22 00:40:00 +00:00
Jim Grosbach
f79f9afb91 Missing piece of the ARM frame index post-scavenging conditionalization 
llvm-svn: 84798
 2009-10-21 23:40:56 +00:00
Jim Grosbach
363a67d9c5 Conditionalize ARM/T2 frame index post-scavenging while working out fixes 
for a few bugs.

llvm-svn: 84791
 2009-10-21 22:59:24 +00:00
Bob Wilson
26a4580439 Most of the NEON shuffle instructions do not support 64-bit element types. 
llvm-svn: 84785
 2009-10-21 21:36:27 +00:00
Jim Grosbach
452de96b04 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.

llvm-svn: 84778
 2009-10-21 20:44:34 +00:00
Bob Wilson
41f94edfb0 Fix NEON VST2LN instruction encoding. 
Patch by Johnny Chen.

llvm-svn: 84767
 2009-10-21 17:54:01 +00:00
Bob Wilson
5f9ea75e2b Revert 84732. It was the wrong fix. 
llvm-svn: 84766
 2009-10-21 17:52:34 +00:00
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Chris Lattner
690911b253 tidy 
llvm-svn: 84738
 2009-10-21 04:10:24 +00:00
Bob Wilson
02d3df4a87 Fix some more NEON instruction encoding problems. 
Thanks to Johnny Chen for discovering the problem.

llvm-svn: 84732
 2009-10-21 02:27:20 +00:00
Bob Wilson
e85a3142bc Leave some NEON instruction encoding bits unspecified instead of setting 
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.

llvm-svn: 84730
 2009-10-21 02:15:46 +00:00