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622 Commits

Author SHA1 Message Date
Sean Callanan
0bc10793b0 Added the rdtscp instruction to the x86 instruction 
tables.

llvm-svn: 96073
 2010-02-13 02:06:11 +00:00
Sean Callanan
9806eade6e Fixed encodings for invlpg, invept, and invvpid. 
llvm-svn: 96065
 2010-02-13 01:48:34 +00:00
Chris Lattner
5b01ab848c remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.

llvm-svn: 96058
 2010-02-13 00:41:14 +00:00
Chris Lattner
f1f926247f enhance the immediate field encoding to know whether the immediate 
is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026
 2010-02-12 22:27:07 +00:00
Chris Lattner
2265d6280b Add support for a union type in LLVM IR. Patch by Talin! 
llvm-svn: 96011
 2010-02-12 20:49:41 +00:00
Daniel Dunbar
c82069746b X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented 
with "tied memory operands", which is wrong.

llvm-svn: 95950
 2010-02-12 01:22:03 +00:00
Chris Lattner
a10c41c6df improve encoding information for branches. We now know they have 
8 or 32-bit immediates, which allows the new encoder to handle
them.

llvm-svn: 95927
 2010-02-11 21:45:31 +00:00
Chris Lattner
4718a3f4ea unbreak the build. 
llvm-svn: 95915
 2010-02-11 19:52:11 +00:00
Chris Lattner
d69e1c1bb2 refactor the conditional jump instructions in the .td file to 
use a multipattern that generates both the 1-byte and 4-byte 
versions from the same defm

llvm-svn: 95901
 2010-02-11 19:25:55 +00:00
Dan Gohman
92b6122204 Fix "the the" and similar typos. 
llvm-svn: 95781
 2010-02-10 16:03:48 +00:00
David Greene
bb211816b6 TableGen fragment refactoring. 
Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files.  We will use this for
the AVX specification to help with the transition from the current
SSE specification.

llvm-svn: 95727
 2010-02-09 23:52:19 +00:00
Chris Lattner
e1b8c529a4 fix incorrect encoding of SBB8mi that Kevin noticed. 
llvm-svn: 95448
 2010-02-05 22:56:11 +00:00
Chris Lattner
9b3cf069dc teach X86MCInstLower to lower the MOV32r0 and MOV8r0 
pseudo instructions.

llvm-svn: 95433
 2010-02-05 21:21:06 +00:00
Chris Lattner
32f09202d6 factor code better in X86MCInstLower::Lower, teach it to 
lower the SETB* instructions.

llvm-svn: 95431
 2010-02-05 21:13:48 +00:00
Kevin Enderby
57859abd72 Added support for X86 instruction prefixes so llvm-mc can assemble them. The 
Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.

llvm-svn: 95252
 2010-02-03 21:04:42 +00:00
Evan Cheng
e86a191862 Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc. 
llvm-svn: 94950
 2010-01-31 07:28:44 +00:00
Daniel Dunbar
23e8bc782c MC/X86 AsmParser: Handle absolute memory operands correctly. We were doing 
something totally broken and parsing them as immediates, but the .td file also
had the wrong match class so things sortof worked. Except, that is, that we
would parse
  movl $0, %eax
as
  movl 0, %eax
Feel free to guess how well that worked.

llvm-svn: 94869
 2010-01-30 01:02:48 +00:00
Daniel Dunbar
ee85d3388b X86.td: Refactor to bring operands that use print_pcrel_imm together. 
llvm-svn: 94861
 2010-01-30 00:24:12 +00:00
Daniel Dunbar
e92f9cffdb AsmMatcher/X86: Separate out sublass for memory operands that have no segment 
register, and use to cleanup a FIXME in X86AsmParser.cpp.

llvm-svn: 94859
 2010-01-30 00:24:00 +00:00
Evan Cheng
bc0b06fb16 Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add patterns first. 
llvm-svn: 93245
 2010-01-12 18:31:19 +00:00
Dan Gohman
51b3e804dc Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. 
llvm-svn: 93229
 2010-01-12 04:42:54 +00:00
Evan Cheng
bd938ebc90 Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. 
llvm-svn: 93191
 2010-01-11 22:03:29 +00:00
Evan Cheng
bc84a42d7b Revert 93158. It's breaking quite a few x86_64 tests. 
llvm-svn: 93185
 2010-01-11 21:13:41 +00:00
Evan Cheng
4548543b0b Do not turn 8-bit OR to ADD since ADD8ri is not 3-addressfiable. 
llvm-svn: 93182
 2010-01-11 20:18:04 +00:00
Dan Gohman
5b79391087 Re-instate MOV64r0 and MOV16r0, with adjustments to work with the 
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.

llvm-svn: 93158
 2010-01-11 17:37:57 +00:00
Dan Gohman
a83443605d Pattern top-level operators don't need to be restricted to a 
single user. The _su forms are intended for non-top-level nodes.

llvm-svn: 93155
 2010-01-11 17:21:05 +00:00
Evan Cheng
ee806a0db5 Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. 
llvm-svn: 93152
 2010-01-11 17:03:47 +00:00
Evan Cheng
4f25f87baa Fix what looks to me obvious instruction definition bugs. 
1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.

llvm-svn: 92985
 2010-01-08 01:29:19 +00:00
Dan Gohman
d3383baab0 Remove the SDNPAssociative properties for the flags-producing 
operators. Eli pointed out that it's not obvious what that
would mean.

llvm-svn: 92555
 2010-01-05 00:44:20 +00:00
Dan Gohman
29583f656d Add SDNPCommutative and SDNPAssociative to several X86 target nodes. 
This lets isel fold loads into them in more cases.

llvm-svn: 92506
 2010-01-04 20:51:05 +00:00
Eli Friedman
3a53d1cb1a PR5886: Make sure IMUL32m is marked as setting EFLAGS, so scheduling doesn't 
do illegal stuff around it.  No testcase because the issue is very fragile.

llvm-svn: 92167
 2009-12-26 20:08:30 +00:00
Chris Lattner
f77ca5f9f5 really remove the instruction, don't just comment it out 
llvm-svn: 91976
 2009-12-23 01:46:40 +00:00
Chris Lattner
d7e8bd73fe completely eliminate the MOV16r0 'instruction'. The only 
interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.

llvm-svn: 91975
 2009-12-23 01:45:04 +00:00
Chris Lattner
dbcf2725aa stop pattern matching 16-bit zero's of a register to MOV16r0, 
instead use the appropriate subreggy thing.  This generates identical
code on some large apps (thanks to Evan's cross class coalescing
stuff he did back in july).  This means that MOV16r0 can go away
completely in the future soon.

llvm-svn: 91972
 2009-12-23 01:30:26 +00:00
Evan Cheng
7cd6bfe549 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
llvm-svn: 91910
 2009-12-22 17:47:23 +00:00
Evan Cheng
d97d025eba On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672
 2009-12-18 07:40:29 +00:00
Sean Callanan
06b6feb2e1 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Evan Cheng
aaf2f58a04 Re-enable 91381 with fixes. 
llvm-svn: 91489
 2009-12-16 00:53:11 +00:00
Evan Cheng
cd8f0de016 Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
llvm-svn: 91381
 2009-12-15 00:53:42 +00:00
Evan Cheng
53e863f152 Fix an obvious bug. No test case since LEA16r is not being used. 
llvm-svn: 91219
 2009-12-12 18:51:56 +00:00
Dan Gohman
e573c59c90 Minor whitespace fixes. 
llvm-svn: 90166
 2009-11-30 23:33:53 +00:00
Dan Gohman
b5ec39e2dc Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. 
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711
 2009-11-23 23:20:51 +00:00
Dan Gohman
3045fc7514 Use a tab in INT3's asm string, for consistency. 
llvm-svn: 86850
 2009-11-11 18:07:16 +00:00
Anton Korobeynikov
9737bfedeb Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
 2009-11-02 00:11:39 +00:00
Dan Gohman
2767aa065e Initial x86 support for BlockAddresses. 
llvm-svn: 85557
 2009-10-30 01:28:02 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Dan Gohman
6b54c70e78 Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too. 
llvm-svn: 84652
 2009-10-20 18:14:49 +00:00
Chris Lattner
cf8c23d554 remove strings from instructions who are never asmprinted. 
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.

llvm-svn: 84526
 2009-10-19 19:51:42 +00:00
Chris Lattner
f34b09b112 remove the asmstring, it is now dead. Improve comment. 
llvm-svn: 82390
 2009-09-20 07:32:00 +00:00
Chris Lattner
d56be552eb kill off printPICLabel now, it's specialness is handled by 
the MachineInstr ->MCInst lowering process, not in the 
asmprinter.

llvm-svn: 82388
 2009-09-20 07:28:26 +00:00