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Author SHA1 Message Date
Simon Pilgrim
0bd59db959 [X86][Atom] Remove unnecessary scalar/vector load/move instrw overrides. 
llvm-svn: 330548
 2018-04-22 16:49:35 +00:00
Sanjay Patel
4de4f60b53 [InstCombine] add vector test with undef elts; NFC 
llvm-svn: 330547
 2018-04-22 15:59:14 +00:00
Simon Pilgrim
237f2154b7 [X86] Fix (completely overridden) WriteFHAdd/WritePHAdd classes to allow us to remove unnecessary instrw overrides. 
llvm-svn: 330546
 2018-04-22 15:25:59 +00:00
Simon Pilgrim
95e7e6933f [X86][MMX][SSE] Tag missed PHADD/PHSUB instructions with WritePHAdd 
llvm-svn: 330545
 2018-04-22 15:02:23 +00:00
Simon Pilgrim
93235e334a [X86] Remove unnecessary WriteFVarBlend/WriteVarBlend InstRW overrides. 
This also fixes some of the ReadAfterLd issues due to InstRW.

llvm-svn: 330544
 2018-04-22 14:43:12 +00:00
Sanjay Patel
dcdc24c017 [InstSimplify, InstCombine] add vector tests with undef elts; NFC 
llvm-svn: 330543
 2018-04-22 14:19:37 +00:00
Simon Pilgrim
89f86ff724 [X86] Fix WriteMPSAD/WritePSADBW values to allow us to remove unnecessary instrw overrides. 
llvm-svn: 330542
 2018-04-22 10:39:16 +00:00
Simon Pilgrim
fcb80e3122 [X86][SandyBridge] Remove unnecessary WritePOPCNTLd overrides by fixing load latency. 
llvm-svn: 330541
 2018-04-22 10:03:52 +00:00
Simon Pilgrim
a96a6505c6 [llvm-mca][X86] Add POPCNT resource test 
llvm-svn: 330540
 2018-04-22 09:58:00 +00:00
Jonas Devlieghere
c1062e3d3c [test] Fix MC/ELF/nocompression.s 
Unbreak the linux build bots:
  http://lab.llvm.org:8011/builders/clang-lld-x86_64-2stage/builds/5165/
  http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/28775
  http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/8227

llvm-svn: 330539
 2018-04-22 08:46:27 +00:00
Jonas Devlieghere
659684fd3b [lli] Fix syntax error: missing ';' 
Fixes build issue on the windows bots:
  error C2143: syntax error: missing ';'

llvm-svn: 330538
 2018-04-22 08:35:00 +00:00
Jonas Devlieghere
44f381c219 [lli] Make error handling more consistent. 
Makes error handling more consistent by using the helpers in support.

llvm-svn: 330537
 2018-04-22 08:02:11 +00:00
Jonas Devlieghere
44196f9fa0 [llvm-mc] Make error handling more consistent. 
Makes error handling more consistent by using the helpers in support.

llvm-svn: 330536
 2018-04-22 08:01:35 +00:00
Jonas Devlieghere
1d9884d205 [Support] Fix prefix logic in WithColor. 
When a prefix is passed, we need to print a colon a space after it, not
just the prefix.

llvm-svn: 330535
 2018-04-22 08:01:01 +00:00
Craig Topper
88b6ab0c0c [X86] Remove an unnecessary HANDLE_OPTIONAL line from the disassembler operand processing. 
llvm-svn: 330534
 2018-04-22 06:40:37 +00:00
Craig Topper
76d325209c [X86] Change TB to PS on LFENCE instruction. 
This matches the other FENCE instructions.

llvm-svn: 330533
 2018-04-22 03:15:02 +00:00
Craig Topper
553c5351a3 [X86] Remove OpSizeIgnore, it's not implemented any differently than OpSizeFixed. 
llvm-svn: 330532
 2018-04-22 01:24:58 +00:00
Craig Topper
73dbe9122e [X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode. 
Improve the error messages to match GNU assembler.

This also allows us to remove the hack from the disassembler table building.

llvm-svn: 330531
 2018-04-22 00:52:02 +00:00
Brian Gesiak
ca9330d23c [bcanalyzer] Recognize more stream types 
Summary:
`llvm-bcanalyzer` prints out the stream type of the file it is
analyzing. If the file begins with the LLVM IR magic number, it reports
a stream type of "LLVM IR". However, any other bitstream format is
reported as "unknown".

Add some checks for two other common bitstream formats: Clang AST
files, which begin with 'CPCH', and Clang serialized diagnostics, which
begin with 'DIAG'.

Test Plan: `check-llvm`

Reviewers: pcc, aprantl, mehdi_amini, davide, george.karpenkov, JDevlieghere

Reviewed By: JDevlieghere

Subscribers: JDevlieghere, bruno, davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D41979

llvm-svn: 330529
 2018-04-21 23:52:04 +00:00
Simon Pilgrim
d08f8d7586 [X86] Strip unnecessary prefetch + vector move/load instrw overrides from scheduler models. 
llvm-svn: 330527
 2018-04-21 21:59:36 +00:00
Jonas Devlieghere
9bdd5c77dc [Support] Add optional prefix to convenience helpers in WithColor. 
Several tools prefix the error/warning/note output with the name of the
tool. One such tool is LLD for example. This commit adds as an optional
'Prefix' argument to the convenience helpers.

llvm-svn: 330526
 2018-04-21 21:36:11 +00:00
Simon Pilgrim
6e2a921b6a [X86] Strip unnecessary WriteCvtF2I instrw overrides from scheduler models. 
llvm-svn: 330525
 2018-04-21 21:16:44 +00:00
Jonas Devlieghere
7dfecec758 [tools] Use WithColor for printing errors. 
Use convenience helpers in WithColor to print errors, warnings and notes
in a few more tools.

llvm-svn: 330524
 2018-04-21 21:11:59 +00:00
Simon Pilgrim
e8dbfa37fc [X86] Strip unnecessary broadcast/shuffle256 instrw overrides from scheduler models. 
llvm-svn: 330523
 2018-04-21 20:45:12 +00:00
Simon Pilgrim
95cf90d64b [X86][AVX] VPERM2F128/VINSERTF128 should be a shuffle256 schedule like VPERM2I128/VINSERTI128 
llvm-svn: 330522
 2018-04-21 20:04:24 +00:00
Simon Pilgrim
1e0e836167 [X86] Strip unnecessary vector integer math, shift-imm, extend, shuffle, pack/unpack instruction instrw overrides from scheduler models. 
llvm-svn: 330521
 2018-04-21 19:11:55 +00:00
Craig Topper
2551d36eb1 [X86] Add DAG combine to turn (trunc (srl (mul ext, ext), 16) into PMULHW/PMULHUW. 
Ultimately I want to use this to remove the intrinsics for these instructions.

llvm-svn: 330520
 2018-04-21 18:39:21 +00:00
Craig Topper
98c137e28f [X86] Add test cases that show the current codegen for (trunc (srl (mul ext, ext), 16)). NFC 
A future patch will turn this into MULHU/MULHS.

llvm-svn: 330519
 2018-04-21 18:39:20 +00:00
Craig Topper
f944131ace [X86] Add SchedWrites for LDMXCSR/STMXCSR. 
llvm-svn: 330517
 2018-04-21 18:07:36 +00:00
Sanjay Patel
c987626376 [InstSimplify] move tests for shifts; NFC 
llvm-svn: 330516
 2018-04-21 16:58:00 +00:00
Sanjay Patel
a01fc5df78 [InstSimplify] move/add/regenerate checks for tests; NFC 
llvm-svn: 330515
 2018-04-21 16:23:47 +00:00
Simon Pilgrim
66bfc0f0fd [X86][Haswell] Strip unnecessary WriteFAdd/WriteFHAdd instruction instrw overrides. 
llvm-svn: 330514
 2018-04-21 16:20:28 +00:00
Simon Pilgrim
271deda8c6 [X86][Broadwell] Remove unnecessary VORPD/VORPS instrw override - missed in D45629 
llvm-svn: 330513
 2018-04-21 16:17:47 +00:00
Simon Pilgrim
a68a77d1c5 [llvm-mca][X86] Add AVX2 resource tests 
llvm-svn: 330512
 2018-04-21 16:12:42 +00:00
Simon Pilgrim
8357308c8a [X86] Strip unnecessary WriteFRcp/WriteFRsqrt instruction instrw overrides from scheduler models. 
The required the default skylake schedules to be updated - these were being completely overriden by the InstRW and the existing values not used at all.

llvm-svn: 330510
 2018-04-21 15:16:59 +00:00
Simon Pilgrim
e04f3a7f11 [X86] Strip unnecessary WriteFShuffle instruction instrw overrides from scheduler models. 
llvm-svn: 330508
 2018-04-21 14:56:56 +00:00
Simon Pilgrim
c7007719dc [llvm-mca][X86] Add SSE resource tests to all models 
llvm-svn: 330506
 2018-04-21 14:16:57 +00:00
Simon Pilgrim
e4fd2b189c [X86][SandyBridge] Strip unnecessary MOVQ/CVT instruction instrw overrides. 
llvm-svn: 330505
 2018-04-21 14:03:40 +00:00
Simon Pilgrim
64c82de81a [X86] Strip unnecessary MMX instruction instrw overrides from scheduler models. 
llvm-svn: 330503
 2018-04-21 12:15:42 +00:00
Simon Pilgrim
a0985965fa [llvm-mca][X86] Add MMX resource tests 
llvm-svn: 330502
 2018-04-21 11:28:59 +00:00
Simon Pilgrim
a859ae93ff [X86] Strip unnecessary x87 instruction instrw overrides from scheduler models. 
llvm-svn: 330501
 2018-04-21 11:25:02 +00:00
Simon Pilgrim
215f1c0fcd [llvm-mca][X86] Add X87 resource tests 
llvm-svn: 330499
 2018-04-21 10:36:19 +00:00
Simon Pilgrim
6e004b917c [X86][X87] Add missing fldlg2 schedule test 
llvm-svn: 330498
 2018-04-21 10:35:04 +00:00
Hiroshi Inoue
0a8b8fc8aa [PowerPC] fix incorrect vectorization of abs() on POWER9 
Vectorized loops with abs() returns incorrect results on POWER9. This patch fixes it.
For example the following code returns negative result if input values are negative though it sums up the absolute value of the inputs.

int vpx_satd_c(const int16_t *coeff, int length) {
  int satd = 0;
  for (int i = 0; i < length; ++i) satd += abs(coeff[i]);
  return satd;
}

This problem causes test failures for libvpx.
For vector absolute and vector absolute difference on POWER9, LLVM generates VABSDUW (Vector Absolute Difference Unsigned Word) instruction or variants.
Since these instructions are for unsigned integers, we need adjustment for signed integers.
For abs(sub(a, b)), we generate VABSDUW(a+0x80000000, b+0x80000000). Otherwise, abs(sub(-1, 0)) returns 0xFFFFFFFF(=-1) instead of 1. For abs(a), we generate VABSDUW(a+0x80000000, 0x80000000).

Differential Revision: https://reviews.llvm.org/D45522

llvm-svn: 330497
 2018-04-21 09:32:17 +00:00
Eli Friedman
6c495ec529 [AArch64] Don't crash trying to resolve __stack_chk_guard. 
In certain cases, the compiler might try to merge __stack_chk_guard with
another global variable.  (Or someone could theoretically define
__stack_chk_guard as an alias.)  In that case, make sure we don't crash.

Differential Revision: https://reviews.llvm.org/D45746

llvm-svn: 330495
 2018-04-21 00:07:46 +00:00
Jessica Paquette
cb7a478192 Fix typo in test (verify-machine-instrs -> verify-machineinstrs) 
llvm-svn: 330494
 2018-04-20 23:37:48 +00:00
Jessica Paquette
f99bed0103 [MachineOutliner] XFAIL machine-outliner-noredzone.ll 
The verifier began complaining about an undefined physical register in this
test. XFAILing for the purposes of getting a bot up while I look into it.

Failure:
http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-expensive/11385/

llvm-svn: 330493
 2018-04-20 23:35:54 +00:00
Shoaib Meenai
791e85376d [ObjCARC] Take BlockColors by const reference. NFC 
llvm-svn: 330489
 2018-04-20 22:14:45 +00:00
Shoaib Meenai
7ab27d194a [ObjCARC] Account for funclet token in storeStrong transform 
When creating a call to storeStrong in ObjCARCContract, ensure the call
gets the correct funclet token, otherwise WinEHPrepare will turn the
call (and all subsequent instructions) into unreachable.

We already have logic to do this for the ARC autorelease elision marker;
factor that out into a common function that's used for both. These are
the only two places in this transform that create call instructions.

Differential Revision: https://reviews.llvm.org/D45857

llvm-svn: 330487
 2018-04-20 22:11:03 +00:00
Simon Pilgrim
ced8f6f655 [llvm-mca][X86] Add MMX/SSE/AES/CLMUL resource SandyBridge tests 
llvm-svn: 330486
 2018-04-20 22:04:11 +00:00