1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
Commit Graph

201232 Commits

Author SHA1 Message Date
Kevin P. Neal
0c24e52a4d [FPEnv] IRBuilder fails to add strictfp attribute
The strictfp attribute is required on all function calls in a function
that is itself marked with the strictfp attribute. The IRBuilder knows
this and has a method for adding the attribute to function call instructions.

If a function being called has the strictfp attribute itself then the
IRBuilder will refuse to add the attribute to the calling instruction
despite being asked to add it. Eliminate this error.

Differential Revision: https://reviews.llvm.org/D84878
2020-08-03 13:25:24 -04:00
Craig Topper
fb9c043569 [X86] Use h-register for final XOR of __builtin_parity on 64-bit targets.
This adds an isel pattern and special XOR8rr_NOREX instruction
to enable the use of h-registers for __builtin_parity. This avoids
a copy and a shift instruction. The NOREX instruction is in case
register allocation doesn't use the matching l-register for some
reason. If a R8-R15 register gets picked instead, we won't be
able to encode the instruction since an h-register can't be used
with a REX prefix.

Fixes PR46954
2020-08-03 10:10:17 -07:00
Mircea Trofin
1cbf2902fb [llvm] Add a parser from JSON to TensorSpec
A JSON->TensorSpec utility we will use subsequently to specify
additional outputs needed for certain training scenarios.

Differential Revision: https://reviews.llvm.org/D84976
2020-08-03 09:49:31 -07:00
Gui Andrade
aa6ea791fa [Utils] Add noundef attribute to vim/emacs/vscode syntax scripts
Differential Revision: https://reviews.llvm.org/D84553
2020-08-03 16:45:35 +00:00
Gui Andrade
23e6a33fdb [MSAN] Instrument freeze instruction by clearing shadow
Freeze always returns a defined value. This also prevents msan from
checking the input shadow, which happened because freeze wasn't
explicitly visited.

Differential Revision: https://reviews.llvm.org/D85040
2020-08-03 16:42:17 +00:00
Florian Hahn
6d82efa764 [SCEV] If Start>=RHS, simplify (Start smin RHS) = RHS for trip counts.
In some cases, it seems like we can get rid of unnecessary s/umins by
using information from the loop guards (unless I am missing something).

One place where this seems to be helpful in practice is when computing
loop trip counts. This patch just changes howManyGreaterThans for now.
Note that this requires a loop for which we can check 'is guarded'.

On SPEC2000/SPEC2006/MultiSource, there are some notable changes for
some programs in the number of loops unrolled and trip counts computed.

```
Same hash: 179 (filtered out)
Remaining: 58
Metric: scalar-evolution.NumTripCountsComputed

Program                                        base    patch   diff
 test-suite...langs-C/compiler/compiler.test    25.00   31.00  24.0%
 test-suite.../Applications/SPASS/SPASS.test   2020.00 2323.00 15.0%
 test-suite...langs-C/allroots/allroots.test    29.00   32.00  10.3%
 test-suite.../Prolangs-C/loader/loader.test    17.00   18.00   5.9%
 test-suite...fice-ispell/office-ispell.test   253.00  265.00   4.7%
 test-suite...006/450.soplex/450.soplex.test   3552.00 3692.00  3.9%
 test-suite...chmarks/MallocBench/gs/gs.test   453.00  470.00   3.8%
 test-suite...ngs-C/assembler/assembler.test    29.00   30.00   3.4%
 test-suite.../Benchmarks/Ptrdist/bc/bc.test   263.00  270.00   2.7%
 test-suite...rks/FreeBench/pifft/pifft.test   722.00  741.00   2.6%
 test-suite...count/automotive-bitcount.test    41.00   42.00   2.4%
 test-suite...0/253.perlbmk/253.perlbmk.test   1417.00 1451.00  2.4%
 test-suite...000/197.parser/197.parser.test   387.00  396.00   2.3%
 test-suite...lications/sqlite3/sqlite3.test   1168.00 1189.00  1.8%
 test-suite...000/255.vortex/255.vortex.test   173.00  176.00   1.7%

Metric: loop-unroll.NumUnrolled

Program                                        base   patch  diff
 test-suite...langs-C/compiler/compiler.test     1.00   3.00 200.0%
 test-suite.../Applications/SPASS/SPASS.test   134.00 234.00 74.6%
 test-suite...count/automotive-bitcount.test     3.00   4.00 33.3%
 test-suite.../Prolangs-C/loader/loader.test     3.00   4.00 33.3%
 test-suite...langs-C/allroots/allroots.test     3.00   4.00 33.3%
 test-suite...Source/Benchmarks/sim/sim.test    10.00  12.00 20.0%
 test-suite...fice-ispell/office-ispell.test    21.00  25.00 19.0%
 test-suite.../Benchmarks/Ptrdist/bc/bc.test    32.00  38.00 18.8%
 test-suite...006/450.soplex/450.soplex.test   300.00 352.00 17.3%
 test-suite...rks/FreeBench/pifft/pifft.test    60.00  69.00 15.0%
 test-suite...chmarks/MallocBench/gs/gs.test    57.00  63.00 10.5%
 test-suite...ngs-C/assembler/assembler.test    10.00  11.00 10.0%
 test-suite...0/253.perlbmk/253.perlbmk.test   145.00 157.00  8.3%
 test-suite...000/197.parser/197.parser.test    43.00  46.00  7.0%
 test-suite...TimberWolfMC/timberwolfmc.test   205.00 214.00  4.4%
 Geomean difference                                           7.6%
```

Fixes https://bugs.llvm.org/show_bug.cgi?id=46939
Fixes https://bugs.llvm.org/show_bug.cgi?id=46924 on X86.

Reviewed By: mkazantsev

Differential Revision: https://reviews.llvm.org/D85046
2020-08-03 17:22:42 +01:00
Cameron McInally
60134c9850 [FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
This patch stops unconditionally transforming FSUB(-0,X) into an FNEG(X) while building the DAG. There is also one small change to handle the new FSUB(-0,X) similarly to FNEG(X) in the AMDGPU backend.

Differential Revision: https://reviews.llvm.org/D84056
2020-08-03 10:22:25 -05:00
Xing GUO
8d54ee8a03 [DWARFYAML] Implement the .debug_loclists section.
This patch implements the .debug_loclists section. There are only two
DWARF expressions are implemented in this patch (DW_OP_consts,
DW_OP_stack_value). We will implement more in the future.

The YAML description of the .debug_loclists section is:

```
debug_loclists:
  - Format:              DWARF32 ## Optional
    Length:              0x1234  ## Optional
    Version:             5       ## Optional (5 by default)
    AddressSize:         8       ## Optional
    SegmentSelectorSize: 0       ## Optional (0 by default)
    OffsetEntryCount:    1       ## Optional
    Offsets:             [ 1 ]   ## Optional
    Lists:
      - Entries:
          - Operator:          DW_LLE_startx_endx
            Values:            [ 0x1234, 0x4321 ]
            DescriptorsLength: 0x1234             ## Optional
            Descriptors:
              - Operator: DW_OP_consts
                Values:   [ 0x1234 ]
```

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D84234
2020-08-03 23:20:15 +08:00
Shinji Okumura
4e0af248b2 [NFC][APInt][DenseMapInfo] Move DenseMapAPIntKeyInfo into DenseMap.h as DenseMapInfo<APInt>
`DenseMapAPIntKeyInfo` is now located in `lib/IR/LLVMContextImpl.h`.
Moved it into `include/ADT/DenseMapInfo.h` to use it.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D85131
2020-08-03 23:31:13 +09:00
Sanjay Patel
7714e21eba [InstCombine] reduce xor-of-or's bitwise logic (PR46955); 2nd try
The 1st try at this (rG2265d01f2a5b) exposed what looks like
unspecified behavior in C/C++ resulting in test variations.

The arguments to BinaryOperator::CreateAnd() were both IRBuilder
function calls, and the order in which they execute determines
the order of the new instructions in the IR. But the order of
function arg evaluation is not fixed by the rules of C/C++, so
depending on compiler config, the test would fail because the
test expected a single fixed ordering of instructions.

Original commit message:
I tried to use m_Deferred() on this, but didn't find
a clean way to do that.

http://bugs.llvm.org/PR46955

https://alive2.llvm.org/ce/z/2h6QTq
2020-08-03 10:21:56 -04:00
Xing GUO
f5eb618063 [DWARFYAML] Offsets should be omitted when the OffsetEntryCount is 0.
The offsets field should be omitted when the 'OffsetEntryCount' entry is
specified to be 0.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D85006
2020-08-03 22:06:08 +08:00
Matt Arsenault
c177fc936f GlobalISel: Handle arbitrary FewerElementsVector for G_IMPLICIT_DEF 2020-08-03 09:14:08 -04:00
Matt Arsenault
7162966fa9 AMDGPU/GlobalISel: Remove old hacks for boolean selection
There were various hacks used to try to avoid making s1 SGPR vs. s1
VCC ambiguous after constraining the register before we had a strategy
to deal with this. This also attempted to handle undef operands, which
are now illegal gMIR.
2020-08-03 09:04:14 -04:00
Matt Arsenault
7371d3a454 GlobalISel: Reimplement moreElementsVectorDst
Use pad with undef and unmerge with unused results. This is annoyingly
similar to several other places in LegalizerHelper, but they're all
slightly different.
2020-08-03 09:03:48 -04:00
Sanjay Patel
695d11fd09 Revert "[InstCombine] reduce xor-of-or's bitwise logic (PR46955)"
This reverts commit 2265d01f2a5bd153959701e22f5be2a40e1674a3.
Seeing bot failures after this change like:
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/42586
2020-08-03 08:58:41 -04:00
Matt Arsenault
59ad55e97d AMDGPU/GlobalISel: Apply load bitcast to s.buffer.load intrinsic
Should also apply this to the non-scalar buffer loads.
2020-08-03 08:54:29 -04:00
Simon Pilgrim
38a46e3c56 [X86][SSE] Start shuffle combining from ANY_EXTEND_VECTOR_INREG on SSE targets
We already do this on AVX (+ for ZERO_EXTEND_VECTOR_INREG), but this enables it for all SSE targets - we attempted something similar back at rL357057 but hit issues with the ZERO_EXTEND_VECTOR_INREG handling (PR41249).

I'm still looking at the vector-mul.ll regression - which is due to 32-bit targets performing the load as a f64, resulting in the shuffle combiner thinking it has to create a shuffle in the float domain.
2020-08-03 13:41:48 +01:00
Matt Arsenault
e7682e1add AMDGPU/GlobalISel: Fix selecting broken copies for s32->s64 anyext
These should probably not be legal in the first place, but that might
also be a pain.
2020-08-03 08:36:41 -04:00
Sanjay Patel
a8fb4d6932 [InstCombine] reduce xor-of-or's bitwise logic (PR46955)
I tried to use m_Deferred() on this, but didn't find
a clean way to do that.

http://bugs.llvm.org/PR46955

https://alive2.llvm.org/ce/z/2h6QTq
2020-08-03 08:31:43 -04:00
Sanjay Patel
ad3d7a2e06 [InstCombine] add tests for xor-of-ors; NFC 2020-08-03 08:31:43 -04:00
Nicholas Guy
a32b9bcdd6 [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz
Fixes a regression caused by D82439, in which IT blocks were no longer being
generated when -Oz is present. This was due to the CPSR register being marked as
dead, while this case was not accounted for.

Differential Revision: https://reviews.llvm.org/D83667
2020-08-03 13:20:32 +01:00
Georgii Rymar
d73aa6dbae [llvm-readobj] - Don't stop dumping when the name of a relocation section can't be read.
This removes undesired `unwrapOrError` calls from printRelocations() methods.

Differential revision: https://reviews.llvm.org/D84408
2020-08-03 14:49:09 +03:00
Georgii Rymar
2f6470d04a [llvm-readobj] - Massive test cases cleanup.
This patch does the following:
1) Starts using YAML macro to reduce the number of YAML documents in tests.
2) Adds `#` before 'RUN'/`CHECK` lines in a few tests where it is missing.
3) Removes unused YAML keys.
4) Starts using `ENTSIZE=<none>` to simplify tests (see D84526).
5) Removes trailing white spaces in a few places.

Differential revision: https://reviews.llvm.org/D85013
2020-08-03 14:07:06 +03:00
Alex Richardson
8a7212b0e5 Fix update_cc_test_checks.py --llvm-bin after D78478
Not passing --clang would result in a python exception after this change:
(TypeError: expected str, bytes or os.PathLike object, not NoneType)
because the --clang argument default was only being populated in the
initial argument parsing pass but not later on.
Fix this by adding an argparse callback to set the default values.

Reviewed By: vitalybuka, MaskRay

Differential Revision: https://reviews.llvm.org/D84511
2020-08-03 11:18:01 +01:00
Tatyana Krasnukha
4bc03c3759 [cmake] Make MSVC generate appropriate __cplusplus macro definition
Differential Revision: https://reviews.llvm.org/D84023
2020-08-03 12:52:43 +03:00
Alex Richardson
cf20fb4e08 Execute llvm-lit with the python found by CMake by default
The check-* targets run ${Python3_EXECUTABLE} $BUILD/bin/llvm-lit, but
running `./bin/llvm-lit $ARGS` from the build directory currently always
uses "python" to run llvm-lit. On most systems this will be python2.7 even
if we found python3 at CMake time.

Reviewed By: compnerd

Differential Revision: https://reviews.llvm.org/D84625
2020-08-03 10:51:35 +01:00
Georgii Rymar
9f706106c9 [llvm-readobj] - Don't call unwrapOrErr in findSectionByName.
We have a `findSectionByName` helper that tries to find a section
by it name. It is used in a few places, but never tested.

I'd like to reuse this helper for a different place.
For this, I've changed it to return Expected<> and now it
doesn't use `unwrapOrErr` anymore. It also now a member of
Dumper class and might report warnings.

Differential revision: https://reviews.llvm.org/D84651
2020-08-03 12:41:00 +03:00
Georgii Rymar
c0d697302e [yaml2obj] - Add a support for "<none>" value for all optional fields.
It implements an approach suggested in the D84398 thread.

With it the following:

```
Sections:
  - Name:   .bar
    Type:   SHT_PROGBITS
    Offset: [[MACRO=<none>]]
```

works just like the `Offset` key was not specified.
It is useful for tests that want to have a default value for a field and to
have a way to override it at the same time.

Differential revision: https://reviews.llvm.org/D84526
2020-08-03 12:27:39 +03:00
Florian Hahn
da4b85138e [LV] Do not check widening decision for instrs outside of loop.
No widening decisions will be computed for instructions outside the
loop. Do not try to get a widening decision. The load/store will be just
a scalar load, so treating at as normal should be fine I think.

Fixes PR46950.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D85087
2020-08-03 10:09:24 +01:00
Xing GUO
d06f3fcac0 [MachOYAML] Remove redundant variable initialization. NFC.
The value of `is64Bit` is initialized in the constructor body.
2020-08-03 16:17:28 +08:00
Shinji Okumura
271e9e67cd [Attributor] Check nonnull attribute violation in AAUndefinedBehavior
This patch makes it possible to handle nonnull attribute violation at callsites in AAUndefinedBehavior.
If null pointer is passed to callee at a callsite and the corresponding argument of callee has nonnull attribute, the behavior of the callee is undefined.
In this patch, violations of argument nonnull attributes is only handled.
But violations of returned nonnull attributes can be handled and I will implement that in a follow-up patch.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D84733
2020-08-03 17:12:50 +09:00
Igor Kudrin
7228215a61 [DebugInfo] Make DIEDelta::SizeOf() more explicit. NFCI.
The patch restricts DIEDelta::SizeOf() to accept only DWARF forms that
are actually used in the LLVM codebase. This should make the use of the
class more explicit and help to avoid issues similar to fixed in D83958
and D84094.

Differential Revision: https://reviews.llvm.org/D84095
2020-08-03 15:04:15 +07:00
Igor Kudrin
46e237eb24 [DebugInfo] Fix misleading using of DWARF forms with DIELabel. NFCI.
DIELabel can emit only 32- or 64-bit values, while it was created in
some places with DW_FORM_udata, which implies emitting uleb128.
Nevertheless, these places also expected to emit U32 or U64, but just
used a misleading DWARF form. The patch updates those places to use more
appropriate DWARF forms and restricts DIELabel::SizeOf() to accept only
forms that are actually used in the LLVM codebase.

Differential Revision: https://reviews.llvm.org/D84094
2020-08-03 15:04:08 +07:00
Igor Kudrin
a1f8fa9c5c [DebugInfo] Fix a comment and a variable name. NFC.
DebugLocListIndex keeps the index of an entry list, not the offset.

Differential Revision: https://reviews.llvm.org/D84093
2020-08-03 15:04:00 +07:00
Igor Kudrin
0a9d458c38 [DebugInfo] Make DIELocList::SizeOf() more explicit. NFCI.
DIELocList is used with a limited number of DWARF forms, see the only
place where it is instantiated, DwarfCompileUnit::addLocationList().

The patch marks the unexpected execution path in DIELocList::SizeOf()
as unreachable, to reduce ambiguity.

Differential Revision: https://reviews.llvm.org/D84092
2020-08-03 15:03:37 +07:00
Djordje Todorovic
635b6d3d23 [NFC] [MIR] Document the reg state flags
This patch adds documentation for the RegState enumeration.

Differential Revision: https://reviews.llvm.org/D84634
2020-08-03 09:03:24 +02:00
Fangrui Song
ac5f15efc8 [CMake] Default ENABLE_X86_RELAX_RELOCATIONS to ON
This makes clang default to -Wa,-mrelax-relocations=yes, which enables
R_386_GOT32X (GNU as enables it regardless of -mrelax-relocations=) and
R_X86_64_[REX_]GOTPCRELX in MC. The produced object files require GNU ld>=2.26
to link. binutils 2.26 is considered a very old release today.
2020-08-02 23:06:31 -07:00
LLVM GN Syncbot
c09cdb2042 [gn build] Port 160ff83765a 2020-08-03 05:55:14 +00:00
Fangrui Song
afa11d8b91 [MC] Default MCAsmBackend::mayNeedRelaxation() to false 2020-08-02 22:13:59 -07:00
QingShan Zhang
4cbe56d2e5 [NFC][PowerPC] Add a multiclass for fsetcc to define them in a uniform way
This is a refactor patch to prepare for adding the support for strict-fsetcc
in PowerPC backend. We want to move their definition into a uniform way so that,
we could add the strict node easier.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D81712
2020-08-03 03:28:03 +00:00
StephenFan
a4e7a84ccb [RISCV] eliminate the repetition declare of SDLoc DL
Differential revision: https://reviews.llvm.org/D85002
2020-08-03 10:24:30 +08:00
Fangrui Song
b2a0487ba4 Reland D64327 [MC][ELF] Allow STT_SECTION referencing SHF_MERGE on REL targets
This drops a GNU gold workaround and reverts the revert commit rL366708.

  Before binutils 2.34, gold -O2 and above did not correctly handle R_386_GOTOFF to
  SHF_MERGE|SHF_STRINGS sections: https://sourceware.org/bugzilla/show_bug.cgi?id=16794

From the original review:

  ... it reduced the size of a big ARM-32 debug image by 33%. It contained ~68M
  of relocations symbols out of total ~71M symbols (96% of symbols table was
  generated for relocations with symbol).

-Wl,-O2 (and -Wl,-O3) is so rare that we should just lower the
optimization level for LLVM_LINKER_IS_GOLD rather than pessimizing all users.
2020-08-02 18:05:17 -07:00
Florian Hahn
4debb5fc67 [Bindings] Remove ipc_propagation.
IPConstantPropagation has been removed, also remove the bindings.
2020-08-02 22:36:53 +01:00
Florian Hahn
5eea1c2f70 Recommit "[IPConstProp] Remove and move tests to SCCP."
This reverts commit 59d6e814ce0e7b40b7cc3ab136b9af2ffab9c6f8.

The cause for the revert (3 clang tests running opt -ipconstprop) was
fixed by removing those lines.
2020-08-02 22:23:54 +01:00
Vitaly Buka
5f096386c6 [StackSafety, NFC] Don't insert empty objects into the map
Result should be the same but it makes generateParamAccessSummary 5x
faster.
2020-08-02 13:58:56 -07:00
Craig Topper
f9f8ff8718 [X86] Use parity flag from byte test/cmp instruction for __builtin_parity when input fits in 8 bits.
If the upper bits of the __builtin_parity idiom are known to be
0 we were previously emitting an xor with 0 to get the parity flag.
But we can use cmp/test instead which may expose opportunities for
load folding or combining an AND.
2020-08-02 10:45:04 -07:00
Craig Topper
ad50e8efd7 [X86] Add test cases for missed opportunity to use a byte test instruction instead of an xor with 0 in parity patterns.
If the input to the ctpop fits in 8 bits, we can use the parity
flag from a TEST instruction, but we're currently XORing with 0.
2020-08-02 10:45:04 -07:00
Simon Pilgrim
3819392568 [AMDGPU] Regenerate tests to fix whitespace indentations
Noticed while updating D77804
2020-08-02 18:11:18 +01:00
Simon Pilgrim
5a07f0ee62 [IR] Add IRBuilderBase::CreateVectorSplat(ElementCount EC) variant
As discussed on D81500, this adds a more general ElementCount variant of the build helper and converts the (non-scalable) unsigned NumElts variant to use it internally.
2020-08-02 16:55:38 +01:00
Sanjay Patel
a4319ccb7e [InstSimplify] fold max (max X, Y), X --> max X, Y
https://alive2.llvm.org/ce/z/VGgG3M
2020-08-02 11:50:58 -04:00