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312 Commits

Author SHA1 Message Date
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Sandeep Patel
1584038783 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
llvm-svn: 84009
 2009-10-13 18:59:48 +00:00
Evan Cheng
241092d89f Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.

llvm-svn: 83197
 2009-10-01 08:22:27 +00:00
Evan Cheng
4dd7d7156e Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
llvm-svn: 83191
 2009-10-01 01:33:39 +00:00
Jim Grosbach
2d057f09e8 Add "isBarrier = 1" to return instructions. 
Patch by Sylvere Teissier.

llvm-svn: 83135
 2009-09-30 01:35:11 +00:00
Evan Cheng
54a1a87862 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo 
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982
 2009-09-28 09:14:39 +00:00
Anton Korobeynikov
189ce11684 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. 
This should be better than single load from constpool.

llvm-svn: 82948
 2009-09-27 23:52:58 +00:00
Evan Cheng
ffe6da0734 Enable pre-regalloc load / store multiple pass for Thumb2. 
llvm-svn: 82893
 2009-09-27 09:46:04 +00:00
David Goodwin
70557af33a RRX reads CPSR. 
llvm-svn: 80699
 2009-09-01 18:32:09 +00:00
Evan Cheng
d53546a6cd Print a nl before pic labels so they start at a new line. This makes assembly more readable. 
llvm-svn: 80350
 2009-08-28 06:59:37 +00:00
Bob Wilson
9482015a0a Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676
 2009-08-21 21:58:55 +00:00
David Goodwin
d57f44783c Update Cortex-A8 instruction itineraries for integer instructions. 
llvm-svn: 79436
 2009-08-19 18:00:44 +00:00
Evan Cheng
d4d2a3d0a6 Fix revsh pattern. 
llvm-svn: 79318
 2009-08-18 05:43:23 +00:00
Evan Cheng
45d6a21e21 Shrink ADR and LDR from constantpool late during constantpool island pass. 
llvm-svn: 78970
 2009-08-14 00:32:16 +00:00
Jim Grosbach
361b7db9bd Add missing defs of R2 and D1. 
llvm-svn: 78918
 2009-08-13 16:59:44 +00:00
David Goodwin
dd797db6bd Finalize itineraries for cortex-a8 integer multiply 
llvm-svn: 78908
 2009-08-13 15:51:13 +00:00
Jim Grosbach
6511e74282 Remove unnecessary newline 
llvm-svn: 78905
 2009-08-13 15:12:16 +00:00
Jim Grosbach
aba7f6b60b Correct comment wording 
llvm-svn: 78904
 2009-08-13 15:11:43 +00:00
David Goodwin
90e7f9873c Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
llvm-svn: 78827
 2009-08-12 18:31:53 +00:00
Jim Grosbach
77d5653945 register naming cleanup (s/ip/r12/) 
llvm-svn: 78806
 2009-08-12 15:21:13 +00:00
Evan Cheng
9302c40108 Remove an Darwin assembler workaround. 
llvm-svn: 78777
 2009-08-12 01:56:42 +00:00
Evan Cheng
783028063e Shrinkify Thumb2 load / store multiple instructions. 
llvm-svn: 78717
 2009-08-11 21:11:32 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Jim Grosbach
67841ae0a8 Add Thumb2 eh_sjlj_setjmp implementation 
llvm-svn: 78701
 2009-08-11 19:42:21 +00:00
Evan Cheng
9fdf9b4435 80 column violation. 
llvm-svn: 78657
 2009-08-11 08:47:46 +00:00
Owen Anderson
b4bce99769 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Evan Cheng
ad380aa97a Add support to reduce most of 32-bit Thumb2 arithmetic instructions. 
llvm-svn: 78550
 2009-08-10 02:37:24 +00:00
Anton Korobeynikov
44fa9f179c Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514
 2009-08-08 23:10:41 +00:00
Evan Cheng
2bdb247c12 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia. 
llvm-svn: 78410
 2009-08-07 21:19:10 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00
David Goodwin
3aafcc1dd2 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
Evan Cheng
e366789b50 Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
llvm-svn: 78126
 2009-08-04 23:47:55 +00:00
Evan Cheng
817618d570 Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. 
llvm-svn: 78030
 2009-08-04 01:41:15 +00:00
Evan Cheng
b9b4b9aa15 Workaround a couple of Darwin assembler bugs. 
llvm-svn: 77781
 2009-08-01 06:13:52 +00:00
Evan Cheng
c165700a7f Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
llvm-svn: 77764
 2009-08-01 01:43:45 +00:00
Evan Cheng
5ef6928dff Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
 2009-08-01 00:16:10 +00:00
Evan Cheng
88a27caaaf Thumb2 movcc need .w suffix. 
llvm-svn: 77743
 2009-07-31 22:21:55 +00:00
David Goodwin
62efc71b9f Darwin assembler now recognizes "orn", so remove workaround. 
llvm-svn: 77627
 2009-07-30 21:51:41 +00:00
David Goodwin
d29f81da16 Darwin assembler now supports "rrx", so remove workaround. 
llvm-svn: 77625
 2009-07-30 21:38:40 +00:00
David Goodwin
30429aef93 Add missing D* register clobbers for Thumb-2 call. 
llvm-svn: 77611
 2009-07-30 18:01:09 +00:00
Evan Cheng
90a1ca6e17 Make sure Thumb2 uses the right call instructions. 
llvm-svn: 77507
 2009-07-29 21:26:42 +00:00
Evan Cheng
c8d3891c87 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500
 2009-07-29 20:10:36 +00:00
Evan Cheng
fc846dd401 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
llvm-svn: 77422
 2009-07-29 02:18:14 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin
0c9e96bf09 Remove support for ORN to workaround <rdar://problem/7096522>. 
llvm-svn: 77363
 2009-07-28 20:51:25 +00:00
David Goodwin
dbc23ece04 Add workaround for <rdar://problem/7098328>. 
llvm-svn: 77340
 2009-07-28 18:15:38 +00:00
David Goodwin
e94d490b89 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
llvm-svn: 77329
 2009-07-28 17:06:49 +00:00
Evan Cheng
b740190d2e - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
David Goodwin
0bcb94eeff ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
llvm-svn: 77275
 2009-07-27 23:34:12 +00:00
David Goodwin
bbab77cdda Thumb-2 does not have RSC. 
llvm-svn: 77201
 2009-07-27 16:39:05 +00:00
David Goodwin
471e9f5b8d Add ".w" suffix for wide thumb-2 instructions. 
llvm-svn: 77199
 2009-07-27 16:31:55 +00:00
Evan Cheng
d615e606c4 Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
 2009-07-25 00:33:29 +00:00
Evan Cheng
84cf748468 Uh. It would be useful to actually print the operand. 
llvm-svn: 77004
 2009-07-24 20:47:38 +00:00
Evan Cheng
e01fec5446 Make sure thumb2 jumptable entries are aligned. 
llvm-svn: 76986
 2009-07-24 18:20:44 +00:00
David Goodwin
85bcdffa4f Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. 
llvm-svn: 76919
 2009-07-24 00:16:18 +00:00
Evan Cheng
90f66e1c4e Thumb2 does not allow the use of "pc" register as part of the load / store address. 
llvm-svn: 76909
 2009-07-23 23:09:51 +00:00
Evan Cheng
8997f6bfc1 Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address. 
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.

llvm-svn: 76889
 2009-07-23 18:26:03 +00:00
David Goodwin
f3c839e0b9 Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. 
llvm-svn: 76883
 2009-07-23 17:06:46 +00:00
Evan Cheng
4a77f28c47 Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
llvm-svn: 76803
 2009-07-22 22:03:29 +00:00
Evan Cheng
34576850e1 Don't forget D16 - D31 are clobbered by calls and sjlj eh. 
llvm-svn: 76729
 2009-07-22 06:46:53 +00:00
David Goodwin
c5ee8fbaa7 CMP and TST define CPSR, not use it. 
llvm-svn: 76489
 2009-07-20 22:13:31 +00:00
Evan Cheng
268b47b1fb Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359
 2009-07-11 06:43:01 +00:00
Evan Cheng
24f2aefc87 Add a thumb2 pass to insert IT blocks. 
llvm-svn: 75218
 2009-07-10 01:54:42 +00:00
Evan Cheng
57a4e81f3f Fix ldm / stm unified syntax; add t2LDM_RET. 
llvm-svn: 75188
 2009-07-09 22:58:39 +00:00
Evan Cheng
3b7c3fafab Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit. 
Note, we are not yet generating these instructions.

llvm-svn: 75181
 2009-07-09 22:21:59 +00:00
Evan Cheng
e08efed97a Correct comment. 
llvm-svn: 75172
 2009-07-09 20:40:44 +00:00
David Goodwin
49fbd8d6b7 Use common code for both ARM and Thumb-2 instruction and register info. 
llvm-svn: 75067
 2009-07-08 23:10:31 +00:00
Evan Cheng
ef49d9c75b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. 
llvm-svn: 75048
 2009-07-08 21:03:57 +00:00
David Goodwin
94209a4c31 Generalize opcode selection in ARMBaseRegisterInfo. 
llvm-svn: 75036
 2009-07-08 20:28:28 +00:00
David Goodwin
5bdef4b3f7 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
llvm-svn: 75010
 2009-07-08 16:09:28 +00:00
Evan Cheng
393e38e44b Add Thumb2 movcc instructions. 
llvm-svn: 74946
 2009-07-07 20:39:03 +00:00
Evan Cheng
fa864ab886 Add Thumb2 pkhbt / pkhtb. 
llvm-svn: 74895
 2009-07-07 05:35:52 +00:00
Evan Cheng
46b98516f6 Add some more Thumb2 multiplication instructions. 
llvm-svn: 74889
 2009-07-07 01:17:28 +00:00
Evan Cheng
5a279bb4b2 Add bfc to armv6t2. 
llvm-svn: 74868
 2009-07-06 22:23:46 +00:00
Evan Cheng
f20e4fba49 Add thumb2 sign / zero extend with rotate instructions. 
llvm-svn: 74755
 2009-07-03 01:43:10 +00:00
Evan Cheng
f3672575d6 Add Thumb2 load / store multiple instructions. Not used yet. 
llvm-svn: 74749
 2009-07-03 00:18:36 +00:00
Evan Cheng
07bcde3709 t2LDR_PRE etc are loads. 
llvm-svn: 74741
 2009-07-03 00:08:19 +00:00
Evan Cheng
162bd9cead Added indexed stores. 
llvm-svn: 74740
 2009-07-03 00:06:39 +00:00
Evan Cheng
fcab8e743a Sign extending pre/post indexed loads. 
llvm-svn: 74736
 2009-07-02 23:16:11 +00:00
Evan Cheng
dad6a41d14 Thumb2 pre/post indexed loads. 
llvm-svn: 74696
 2009-07-02 07:28:31 +00:00
Evan Cheng
57bb186a0c Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate. 
llvm-svn: 74692
 2009-07-02 06:38:40 +00:00
David Goodwin
19aa5c7d51 Add PIC load and store patterns for Thumb-2. 
llvm-svn: 74577
 2009-07-01 00:01:13 +00:00
David Goodwin
aa1f876954 Thumb-2 load and store double description. But nothing yet creates them. 
llvm-svn: 74566
 2009-06-30 22:50:01 +00:00
David Goodwin
5805e9aef5 Add thumb-2 store word, halfword, and byte. 
llvm-svn: 74555
 2009-06-30 22:11:34 +00:00
David Goodwin
aad223dd8a Improve Thumb-2 jump table support. 
llvm-svn: 74549
 2009-06-30 19:50:22 +00:00
David Goodwin
5545d82866 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. 
llvm-svn: 74543
 2009-06-30 18:04:13 +00:00
Evan Cheng
2a527c3419 A few more load instructions. 
llvm-svn: 74500
 2009-06-30 02:15:48 +00:00
David Goodwin
4f53387d26 Add Thumb-2 support for TEQ amd TST. 
llvm-svn: 74468
 2009-06-29 22:49:42 +00:00
David Goodwin
9e1280adf3 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. 
llvm-svn: 74423
 2009-06-29 15:33:01 +00:00
Evan Cheng
093adf3ff9 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
 2009-06-29 07:51:04 +00:00
Evan Cheng
817712377a Renaming for consistency. 
llvm-svn: 74368
 2009-06-27 02:26:13 +00:00
David Goodwin
e1979dfbf5 Remove outdated comment. 
llvm-svn: 74357
 2009-06-26 23:39:02 +00:00
David Goodwin
90fc344e41 When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not. 
llvm-svn: 74355
 2009-06-26 23:13:13 +00:00
David Goodwin
9da977f216 Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc". 
llvm-svn: 74321
 2009-06-26 20:45:56 +00:00
David Goodwin
46eb5a7a2d ADC used to implement adde should use "adcs" opcode instead of "adc". 
llvm-svn: 74293
 2009-06-26 18:07:25 +00:00
David Goodwin
877790aa5f Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI. 
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288
 2009-06-26 16:10:07 +00:00
Evan Cheng
4f0e461e97 Mark a bunch of instructions commutable. 
llvm-svn: 74237
 2009-06-26 00:19:44 +00:00
Evan Cheng
4ac765118d Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. 
llvm-svn: 74228
 2009-06-25 23:34:10 +00:00
David Goodwin
74414108e9 Use MVN for ~t2_so_imm immediates. 
llvm-svn: 74223
 2009-06-25 23:11:21 +00:00
Evan Cheng
0cced3daa8 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 
llvm-svn: 74200
 2009-06-25 20:59:23 +00:00
Evan Cheng
a3be8cba60 Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag. 
llvm-svn: 74158
 2009-06-25 02:08:06 +00:00
Evan Cheng
e31583bf2a Add thumb2 add sp. 
llvm-svn: 74156
 2009-06-25 01:21:30 +00:00
Evan Cheng
e8c58ee743 Add Thumb2 pc relative add. 
llvm-svn: 74141
 2009-06-24 23:47:58 +00:00
Evan Cheng
4dcc3bd23b Test instructions operands were printed in the wrong order. 
llvm-svn: 73990
 2009-06-23 19:56:37 +00:00
Evan Cheng
eaad82627b Proper patterns for thumb2 shift and rotate instructions. 
llvm-svn: 73987
 2009-06-23 19:39:13 +00:00
Evan Cheng
b7077f2943 Rename SelectShifterOperand to SelectThumb2ShifterOperandReg. 
llvm-svn: 73975
 2009-06-23 18:14:38 +00:00
Evan Cheng
73e4b03dc8 Obvious typo. 
llvm-svn: 73967
 2009-06-23 17:54:26 +00:00
Evan Cheng
3e8033f7f7 Initial Thumb2 support. Majority of the work is done by David Goodwin. There are 
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.

I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.

Test cases will be contributed later after I re-organize what's in svn first.

llvm-svn: 73965
 2009-06-23 17:48:47 +00:00
Evan Cheng
92a49d75e4 Replace isTwoAddress with operand constraint. 
llvm-svn: 73947
 2009-06-23 05:23:49 +00:00
Anton Korobeynikov
dbb79a8409 Fix asm string from MOVi16 
llvm-svn: 73661
 2009-06-17 23:43:36 +00:00
Anton Korobeynikov
7fd29c57a8 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

llvm-svn: 73622
 2009-06-17 18:13:58 +00:00
Anton Korobeynikov
4f5b1ef545 Add placeholder for thumb2 stuff 
llvm-svn: 72593
 2009-05-29 23:41:08 +00:00