Evan Cheng
9f27046dc9
- movlp{s|d} and movhp{s|d} support.
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- Normalize shuffle nodes so result vector lower half elements come from the
first vector, the rest come from the second vector. (Except for the
exceptions :-).
- Other minor fixes.
llvm-svn: 27474
2006-04-06 23:23:56 +00:00
Evan Cheng
6d470008c8
Support for comi / ucomi intrinsics.
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llvm-svn: 27444
2006-04-05 23:38:46 +00:00
Evan Cheng
056e0af55a
Handle canonical form of e.g.
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vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 07:20:06 +00:00
Evan Cheng
d562dfa0db
Bogus assert
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llvm-svn: 27434
2006-04-05 06:11:20 +00:00
Evan Cheng
9e56e97205
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
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llvm-svn: 27433
2006-04-05 06:09:26 +00:00
Evan Cheng
849a726354
Handle v8i16 shuffle that must be broken into a pair of pshufhw / pshuflw.
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llvm-svn: 27427
2006-04-05 01:47:37 +00:00
Evan Cheng
7ff32cd571
Use movlpd to: store lower f64 extracted from v2f64.
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Use movhpd to: store upper f64 extracted from v2f64.
llvm-svn: 27382
2006-04-03 22:30:54 +00:00
Evan Cheng
169240beb7
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
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- Some bug fixes and naming inconsistency fixes.
llvm-svn: 27377
2006-04-03 20:53:28 +00:00
Evan Cheng
4623ebd3d0
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
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INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.
llvm-svn: 27314
2006-03-31 21:55:24 +00:00
Evan Cheng
7b9a0c6d7a
Add support to use pextrw and pinsrw to extract and insert a word element
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from a 128-bit vector.
llvm-svn: 27304
2006-03-31 19:22:53 +00:00
Evan Cheng
4ca9bbc1bb
Expand all INSERT_VECTOR_ELT (obviously bad) for now.
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llvm-svn: 27275
2006-03-31 01:30:39 +00:00
Evan Cheng
5d9fc9fdd0
Typo
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llvm-svn: 27272
2006-03-31 00:33:57 +00:00
Evan Cheng
c55052da81
Ok for vector_shuffle mask to contain undef elements.
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llvm-svn: 27271
2006-03-31 00:30:29 +00:00
Evan Cheng
d3c692650f
Make sure all possible shuffles are matched.
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Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.
llvm-svn: 27259
2006-03-30 19:54:57 +00:00
Evan Cheng
7bc3bc8246
- Added some SSE2 128-bit packed integer ops.
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- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.
llvm-svn: 27252
2006-03-29 23:07:14 +00:00
Evan Cheng
d0d3eade59
Need to special case splat after all. Make the second operand of splat
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vector_shuffle undef.
llvm-svn: 27250
2006-03-29 19:02:40 +00:00
Evan Cheng
02b5de9b3e
- More shuffle related bug fixes.
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- Whenever possible use ops of the right packed types for vector shuffles /
splats.
llvm-svn: 27246
2006-03-29 03:04:49 +00:00
Evan Cheng
5194a37602
- Only use pshufd for v4i32 vector shuffles.
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- Other shuffle related fixes.
llvm-svn: 27244
2006-03-29 01:30:51 +00:00
Evan Cheng
178e36174a
Fixing buggy code.
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llvm-svn: 27239
2006-03-28 23:41:33 +00:00
Jim Laskey
fa6dfa9212
Added missing paren on behalf of Ramana Radhakrishnan.
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llvm-svn: 27223
2006-03-28 10:17:11 +00:00
Evan Cheng
0305cec743
Missed X86::isUNPCKHMask
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llvm-svn: 27222
2006-03-28 08:27:15 +00:00
Evan Cheng
fb4b2bfc7d
* Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
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* Bug fixes.
llvm-svn: 27218
2006-03-28 06:50:32 +00:00
Evan Cheng
4d554dae17
- Clean up / consoladate various shuffle masks.
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- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.
llvm-svn: 27210
2006-03-28 02:43:26 +00:00
Evan Cheng
d8d7ec47bd
Model unpack lower and interleave as vector_shuffle so we can lower the
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intrinsics as such.
llvm-svn: 27200
2006-03-28 00:39:58 +00:00
Evan Cheng
0865274fa5
Use pcmpeq to generate vector of all ones.
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llvm-svn: 27167
2006-03-27 07:00:16 +00:00
Nate Begeman
3d518334b9
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
Evan Cheng
1dfbede1d1
Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups
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llvm-svn: 27150
2006-03-26 09:53:12 +00:00
Evan Cheng
e5807f6b47
Build arbitrary vector with more than 2 distinct scalar elements with a
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series of unpack and interleave ops.
llvm-svn: 27119
2006-03-25 09:37:23 +00:00
Evan Cheng
234090b386
Added 128-bit packed integer subtraction.
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llvm-svn: 27096
2006-03-25 01:33:37 +00:00
Evan Cheng
bdb85b387f
Support for scalar to vector with zero extension.
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llvm-svn: 27091
2006-03-24 23:15:12 +00:00
Evan Cheng
d58d54cf3e
Handle BUILD_VECTOR with all zero elements.
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llvm-svn: 27056
2006-03-24 07:29:27 +00:00
Chris Lattner
ace2d0d227
Gabor points out that we can't spell. :)
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llvm-svn: 27049
2006-03-24 07:12:19 +00:00
Evan Cheng
8507228441
All v2f64 shuffle cases can be handled.
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llvm-svn: 27044
2006-03-24 06:40:32 +00:00
Evan Cheng
3028b04057
More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.
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llvm-svn: 27040
2006-03-24 02:58:06 +00:00
Evan Cheng
68410804f0
Handle more shuffle cases with SHUFP* instructions.
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llvm-svn: 27024
2006-03-24 01:18:28 +00:00
Evan Cheng
daa75ed684
Typo
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llvm-svn: 26997
2006-03-23 20:26:04 +00:00
Evan Cheng
5f7cf963db
Add 128-bit integer vector load and add (for testing).
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llvm-svn: 26967
2006-03-23 01:57:24 +00:00
Evan Cheng
54215cd1ea
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
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64-bit vector shuffle.
llvm-svn: 26964
2006-03-22 22:07:06 +00:00
Evan Cheng
7cb4e14749
Some clean up.
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llvm-svn: 26957
2006-03-22 19:22:18 +00:00
Evan Cheng
ae6a39ea92
- Supposely movlhps is faster / better than unpcklpd.
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- Don't forget pshufd is only available with sse2.
llvm-svn: 26956
2006-03-22 19:16:21 +00:00
Evan Cheng
cff38e19c3
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
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splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
llvm-svn: 26954
2006-03-22 18:59:22 +00:00
Evan Cheng
f6dc0a7f5e
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
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PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
llvm-svn: 26951
2006-03-22 08:01:21 +00:00
Chris Lattner
1554bf155e
fix a warning
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llvm-svn: 26941
2006-03-22 04:18:34 +00:00
Evan Cheng
7aac4350c7
Some splat and shuffle support.
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llvm-svn: 26940
2006-03-22 02:53:00 +00:00
Evan Cheng
47dd756c72
- Use movaps to store 128-bit vector integers.
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- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
Chris Lattner
31a93c7740
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
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llvm-svn: 26930
2006-03-21 20:51:05 +00:00
Chris Lattner
09ede9ec9f
Add a build_vector node
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llvm-svn: 26895
2006-03-20 06:18:01 +00:00
Chris Lattner
1bd0aaf2b8
rename these nodes
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llvm-svn: 26848
2006-03-19 01:13:28 +00:00
Evan Cheng
f4774c9091
Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
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llvm-svn: 26833
2006-03-17 20:31:41 +00:00
Chris Lattner
647503bccc
Disable x86 fastcc from passing args in registers
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llvm-svn: 26824
2006-03-17 17:27:47 +00:00