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8309 Commits

Author SHA1 Message Date
Dan Gohman
227e702cae Fix a tokenfactor node to use the load chain rather than the 
load value. This fixes PR2177.

llvm-svn: 48932
 2008-03-28 23:45:16 +00:00
Evan Cheng
10d0aba260 Backing out 48911 for now. It's breaking stuff. 
llvm-svn: 48922
 2008-03-28 17:49:06 +00:00
Evan Cheng
3b54c5fa08 New entry. 
llvm-svn: 48912
 2008-03-28 07:07:06 +00:00
Evan Cheng
d66e48366f Load from stub is already re-materializable. 
llvm-svn: 48911
 2008-03-28 06:49:25 +00:00
Evan Cheng
e66720fd57 Code clean up. 
llvm-svn: 48856
 2008-03-27 01:45:11 +00:00
Evan Cheng
aca67f0b29 Allow certain lea instructions to be rematerialized. 
llvm-svn: 48855
 2008-03-27 01:41:09 +00:00
Evan Cheng
1afaf3092f Remove an unused command line option. 
llvm-svn: 48854
 2008-03-27 01:30:24 +00:00
Roman Levenstein
55b8822511 Use a linked data structure for the uses lists of an SDNode, just like 
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.

The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.

On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better. 

llvm-svn: 48822
 2008-03-26 12:39:26 +00:00
Evan Cheng
6323ea8467 Fix some SSE4.1 instruction encoding bugs. 
llvm-svn: 48815
 2008-03-26 08:11:49 +00:00
Dale Johannesen
8c1e95810f Use ## for comment delimiter on darwin x86-32, so 
llvm's output .s files will go through gcc -std=c99
without triggering preprocesser errors.  Approach
suggested by Daveed Vandevoorde.

llvm-svn: 48808
 2008-03-25 23:29:30 +00:00
Evan Cheng
6226a78cb1 Smaller function alignment when optimizing for size. 
llvm-svn: 48805
 2008-03-25 22:29:46 +00:00
Evan Cheng
6ee0633a42 Rename option -optimizefor-size to -optimize-size. 
llvm-svn: 48804
 2008-03-25 22:28:39 +00:00
Dan Gohman
2b96ce84aa Add explicit keywords. 
llvm-svn: 48801
 2008-03-25 22:06:05 +00:00
Dan Gohman
22002efa15 A quick nm audit turned up several fixed tables and objects that were 
marked read-write. Use const so that they can be allocated in a
read-only segment.

llvm-svn: 48800
 2008-03-25 21:45:14 +00:00
Devang Patel
71f3156ea3 Add optimize-for-size knob. 
llvm-svn: 48793
 2008-03-25 21:02:35 +00:00
Dan Gohman
58ad056286 Add CMP32mr and friends to the load-unfolding table. Among 
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.

llvm-svn: 48777
 2008-03-25 16:53:19 +00:00
Evan Cheng
3da2a15397 Add \t after .set. Fix by Jay Freeman. 
llvm-svn: 48753
 2008-03-24 23:36:49 +00:00
Bill Wendling
2097b72649 Use the bit size of the operand instead of the hard-coded 32 to generate the 
mask.

llvm-svn: 48750
 2008-03-24 23:16:37 +00:00
Evan Cheng
dbdf48276a - SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction. 
llvm-svn: 48746
 2008-03-24 21:52:23 +00:00
Evan Cheng
14c5714421 Remove duplicated entries. 
llvm-svn: 48714
 2008-03-23 22:56:07 +00:00
Anton Korobeynikov
49574852c1 Minor typo fixes. Also add another FIXME. 
llvm-svn: 48710
 2008-03-23 20:32:06 +00:00
Anton Korobeynikov
7a1df26c95 Add license header 
llvm-svn: 48707
 2008-03-23 14:53:18 +00:00
Anton Korobeynikov
005dbb191c Add Win64 compilation callback. This allows easy examples to be JITed on Win64! 
llvm-svn: 48706
 2008-03-23 14:44:32 +00:00
Anton Korobeynikov
e07c433652 Provide a JIT selector on win64 
llvm-svn: 48704
 2008-03-23 13:43:47 +00:00
Anton Korobeynikov
8fda34a926 Hack out the PIC mode on Win64 targets. This needs to be investigated later. 
llvm-svn: 48703
 2008-03-23 13:41:18 +00:00
Anton Korobeynikov
7c5f998b22 Code cleanup. Provide generic way of selecting JIT pointer bitwidth regardless 
of compiler used.

llvm-svn: 48702
 2008-03-23 13:40:45 +00:00
Anton Korobeynikov
23d188b49c Remove old-standing obsolete code. 
llvm-svn: 48701
 2008-03-23 12:32:54 +00:00
Anton Korobeynikov
95f522419c Honour built-in defines on win64 targets for automatically subtarget recognize. 
Force stack alignment to 16 bytes on win targets.

llvm-svn: 48695
 2008-03-22 21:18:22 +00:00
Anton Korobeynikov
befd472d5e Recognize "windows" in target triple, not only "win32" 
llvm-svn: 48694
 2008-03-22 21:12:53 +00:00
Anton Korobeynikov
dbde70d7d6 Add information about callee-saved registers on Win64 
llvm-svn: 48692
 2008-03-22 21:04:01 +00:00
Anton Korobeynikov
dad919f561 Add convenient helper for win64 check. Simplify things slightly. 
llvm-svn: 48691
 2008-03-22 20:57:27 +00:00
Anton Korobeynikov
27c8ad4020 Initial support for Win64 calling conventions. Still in early state. 
llvm-svn: 48690
 2008-03-22 20:37:30 +00:00
Anton Korobeynikov
4b85ece1ab Another comments fixing 
llvm-svn: 48683
 2008-03-22 07:53:40 +00:00
Chris Lattner
308a452c90 Restore this assert now that the livevar bug is fixed. 
This verifies kill info for "ret" fp operands is right.

llvm-svn: 48656
 2008-03-21 20:41:27 +00:00
Duncan Sands
4153fc30c9 Introduce a new node for holding call argument 
flags.  This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines.  There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness.  As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.

llvm-svn: 48640
 2008-03-21 09:14:45 +00:00
Chris Lattner
edfc239ced remove Evan's "ugly hack" that sorta attempted to get 
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.

llvm-svn: 48635
 2008-03-21 06:50:21 +00:00
Chris Lattner
8a4fa95cae Add support for calls that return two FP values in 
ST(0)/ST(1).

llvm-svn: 48634
 2008-03-21 06:38:26 +00:00
Chris Lattner
933d0d318b disable a bogus assertion. 
llvm-svn: 48633
 2008-03-21 06:01:05 +00:00
Chris Lattner
260473f983 Enable support for returning two long-double values in ST(0)/ST(1). 
This allows us to compile fp-stack-2results.ll into:

_test:
	fldz
	fld1
	ret

which returns 1 in ST(0) and 0 in ST(1).  This is needed for x86-64
_Complex long double.

llvm-svn: 48632
 2008-03-21 05:57:20 +00:00
Evan Cheng
4ae9fee64c Undo 48570. Correctly match mmx shift instructions with an immediate operand. 
llvm-svn: 48627
 2008-03-21 00:40:09 +00:00
Chris Lattner
f166a78d79 add a note. 
llvm-svn: 48583
 2008-03-20 04:46:13 +00:00
Evan Cheng
8ecb189245 Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m))) 
llvm-svn: 48578
 2008-03-20 02:18:41 +00:00
Chris Lattner
6c4486c5c7 detabify llvm, patch by Mike Stump! 
llvm-svn: 48577
 2008-03-20 01:22:40 +00:00
Scott Michel
e747d20130 Add more patterns to match in the integer comparison test harnesses. 
Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.

llvm-svn: 48575
 2008-03-20 00:51:36 +00:00
Evan Cheng
6f729b2820 Add intrinsics to match mmx shift builtin's with immediate operand. 
llvm-svn: 48569
 2008-03-19 23:38:52 +00:00
Devang Patel
5e8cbbea65 PassInfo keep tracks whether a pass is an analysis pass or not. 
llvm-svn: 48554
 2008-03-19 21:56:59 +00:00
Dan Gohman
c9dec33f3f Add support for multiple return values for the PPC target by 
converting call result lowering to use the CallingConvLowering
infastructure.

llvm-svn: 48552
 2008-03-19 21:39:28 +00:00
Arnold Schwaighofer
19a78545d9 Don't loose incoming argument registers. Fix documentation style. 
llvm-svn: 48545
 2008-03-19 16:39:45 +00:00
Christopher Lamb
958b0494c3 Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491. 
llvm-svn: 48542
 2008-03-19 08:30:06 +00:00
Bill Wendling
7ae70d6441 On Darwin, GCC issues a ".globl" for something that has a "visibility protected" 
attribute instead of ".protected".

llvm-svn: 48516
 2008-03-18 23:38:12 +00:00
Evan Cheng
5ac87b837e Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it! 
llvm-svn: 48515
 2008-03-18 23:36:35 +00:00
Dale Johannesen
861708b8bb Make Complex long long/double/long double work 
in ppc64 mode.

llvm-svn: 48459
 2008-03-17 17:11:08 +00:00
Chris Lattner
c0ac2481af Check in some #ifdef'd out code switching call argument 
lowering over to SparcCallingConv.td.  We can't make the switch
yet because we can't say to pass f64 registers in 2 x i32 registers
with the td file yet.

llvm-svn: 48449
 2008-03-17 06:58:37 +00:00
Chris Lattner
98f1bf9d41 minor cleanups 
llvm-svn: 48448
 2008-03-17 06:57:02 +00:00
Evan Cheng
07643ce604 Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF. 
llvm-svn: 48447
 2008-03-17 06:56:52 +00:00
Chris Lattner
40ba51c972 remove dead code 
llvm-svn: 48445
 2008-03-17 06:04:10 +00:00
Chris Lattner
fa003f7a57 Switch sparc from using LowerCallTo to using LowerOperation(CALL) like 
other targets.  Use autogenerated calling conv to lower result of
calls.

llvm-svn: 48444
 2008-03-17 06:01:07 +00:00
Chris Lattner
3098125c84 Start moving sparc to use SparcCallingConv.td, switching over 
return lowering first.  This fixes a bug where the top and bottom
of i64 values were returned in the wrong registers before.

llvm-svn: 48443
 2008-03-17 05:41:48 +00:00
Chris Lattner
5cb886d4d6 split sparc lowering out into SparcISelLowering.{cpp|h} to follow 
best practices.

llvm-svn: 48442
 2008-03-17 03:21:36 +00:00
Chris Lattner
5aef54c950 refactor the LowerOperation code out to individual functions for 
each lowering, which is 'best practice'.

llvm-svn: 48441
 2008-03-17 02:52:07 +00:00
Dale Johannesen
ee1e5be870 Next round of PPC32 ABI changes. Allow for gcc 
behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be.  Handle complex long long
and complex double (4 and 8 return regs).

llvm-svn: 48439
 2008-03-17 02:13:43 +00:00
Chris Lattner
dc9bf8fda9 various rotate fun. 
llvm-svn: 48438
 2008-03-17 01:47:51 +00:00
Nate Begeman
f9691b8236 Add a couple missing SSE4 instructions 
llvm-svn: 48430
 2008-03-16 21:14:46 +00:00
Gordon Henriksen
04a60ddcd2 C and Objective Caml bindings for the TargetData class. 
llvm-svn: 48422
 2008-03-16 20:08:03 +00:00
Christopher Lamb
b4f4b41048 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. 
llvm-svn: 48412
 2008-03-16 03:12:01 +00:00
Evan Cheng
9af68f56c5 Remove isImplicitDef TargetInstrDesc flag. 
llvm-svn: 48381
 2008-03-15 00:19:36 +00:00
Evan Cheng
11d2c09adc Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
llvm-svn: 48380
 2008-03-15 00:03:38 +00:00
Dale Johannesen
6195ace4c0 Implement the real calling convention for ppc32 Altivec: 
vectors go at the end of the memory area, after all
non-vector parameters.

llvm-svn: 48364
 2008-03-14 17:41:26 +00:00
Evan Cheng
877c5ecabd Fix some 80 col violations. 
llvm-svn: 48361
 2008-03-14 07:46:48 +00:00
Evan Cheng
fc6645a382 Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8). 
llvm-svn: 48360
 2008-03-14 07:39:27 +00:00
Evan Cheng
6ef1ca4e87 Add debugging stuff. 
llvm-svn: 48359
 2008-03-14 07:13:42 +00:00
Chris Lattner
c60749aa4c Add an issue that is preventing instcombine from doing a simplification. 
llvm-svn: 48356
 2008-03-14 06:00:19 +00:00
Dan Gohman
6a74c23363 Use SDTNone instead of duplicating it. 
llvm-svn: 48346
 2008-03-13 23:07:40 +00:00
Christopher Lamb
0f1c32eb63 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
 2008-03-13 05:47:01 +00:00
Dale Johannesen
1e54f7c2b6 Do not promote float params to double in varargs 
calls here.  This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.

llvm-svn: 48310
 2008-03-12 23:40:01 +00:00
Chris Lattner
7925cc72c0 Reimplement the parameter attributes support, phase #1. hilights: 
1. There is now a "PAListPtr" class, which is a smart pointer around
   the underlying uniqued parameter attribute list object, and manages
   its refcount.  It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
   the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
   longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
   ParamAttrsWithIndex's, no need to make a SmallVector of a specific 
   size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
   dereferencing the pointer is simplified to just access the 
   PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
   bit simpler.

Phase #2 will rename some stuff (e.g. PAListPtr) and do other less 
invasive changes.

llvm-svn: 48289
 2008-03-12 17:45:29 +00:00
Evan Cheng
df92afe7d3 Clean up my own mess. 
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.

llvm-svn: 48279
 2008-03-12 07:02:50 +00:00
Dale Johannesen
19b4c2dfaf One more bit of Altivec parameter passing. 
llvm-svn: 48269
 2008-03-12 00:49:20 +00:00
Dale Johannesen
460dc31418 Implement Altivec passing to varargs functions on ppc. 
llvm-svn: 48264
 2008-03-12 00:22:17 +00:00
Anton Korobeynikov
55f54ba252 Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137 
llvm-svn: 48257
 2008-03-11 22:38:53 +00:00
Dan Gohman
8e3c88c4e9 Use PassManagerBase instead of FunctionPassManager for functions 
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.

llvm-svn: 48256
 2008-03-11 22:29:46 +00:00
Chris Lattner
fd2c24af72 Implement basic support for the 'f' register class constraint. This basically 
works, but probably won't if you mix it with 't' or 'u' yet.

llvm-svn: 48243
 2008-03-11 19:50:13 +00:00
Chris Lattner
4458eecb7a coalesce away 80-bit floating point copies. 
llvm-svn: 48241
 2008-03-11 19:30:09 +00:00
Chris Lattner
aa2287714e convert a massive if statement to a switch. 
llvm-svn: 48240
 2008-03-11 19:28:17 +00:00
Chris Lattner
b3fefb1e5c start handling the 'f' x87 constraint. 
llvm-svn: 48239
 2008-03-11 19:06:29 +00:00
Christopher Lamb
4d5034cf91 Missed part of recommit. 
llvm-svn: 48224
 2008-03-11 10:27:36 +00:00
Christopher Lamb
74f4d837df Recommitting parts of r48130. These do not appear to cause the observed failures. 
llvm-svn: 48223
 2008-03-11 10:09:17 +00:00
Evan Cheng
318a01e5fb If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_). 
llvm-svn: 48220
 2008-03-11 07:54:14 +00:00
Evan Cheng
af1c76846d When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. 
llvm-svn: 48218
 2008-03-11 07:19:34 +00:00
Evan Cheng
53213ba056 In 32-bit mode, mark 64-bit GPR's as unallocatable. 
llvm-svn: 48217
 2008-03-11 07:16:00 +00:00
Nick Lewycky
02e4d6f2dd Fix the build on gcc 4.2. 
llvm-svn: 48212
 2008-03-11 05:56:09 +00:00
Chris Lattner
9826c9365e Change the model for FP Stack return to use fp operands on the 
RET instruction instead of using FpSET_ST0_32.  This also generalizes
the code to handling returning of multiple FP results.

llvm-svn: 48209
 2008-03-11 03:23:40 +00:00
Dan Gohman
85bfbe2293 Generalize ExpandIntToFP to handle the case where the operand is legal 
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type. 

llvm-svn: 48206
 2008-03-11 01:59:03 +00:00
Chris Lattner
d1a014af4e abort with an assert instead of a cerr to get line# 
llvm-svn: 48199
 2008-03-10 23:56:08 +00:00
Scott Michel
599ff689d0 - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency. 
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.

llvm-svn: 48197
 2008-03-10 23:49:09 +00:00
Chris Lattner
f0684bfd16 Don't emit FP_REG_KILL into a block that just returns. Nothing 
can be live out of the block anyway, so it isn't needed.

llvm-svn: 48192
 2008-03-10 23:34:12 +00:00
Dale Johannesen
3278acdaaa Disable prolog code that aligns the stack when a 
local object of >16 byte alignment exists.  It does not
work and getting it to work is not trivial, as explained
in the comment.  This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.

(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec.  So I think disabling it is OK.)

llvm-svn: 48188
 2008-03-10 22:59:46 +00:00
Bill Wendling
80bc045af5 Change the "enable/disable" mechanism so that we can enable PPC register 
scavenging for 32-bit and 64-bit separately.

llvm-svn: 48186
 2008-03-10 22:49:16 +00:00
Chris Lattner
d393772580 Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to 
copyfromreg/copytoreg instead.

llvm-svn: 48174
 2008-03-10 21:08:41 +00:00
Evan Cheng
7d9e5a7680 Default ISD::PREFETCH to expand. 
llvm-svn: 48169
 2008-03-10 19:38:10 +00:00
Evan Cheng
067ecbc341 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. 
llvm-svn: 48167
 2008-03-10 19:31:26 +00:00
Chris Lattner
52be2c645e fix 80 col violations. 
llvm-svn: 48166
 2008-03-10 18:55:53 +00:00
Nicolas Geoffray
a904844534 Stylistic modifications. No functionality changes. 
llvm-svn: 48158
 2008-03-10 17:46:45 +00:00
Scott Michel
38f8a1043a Integer comparison tests for CellSPU. 
llvm-svn: 48152
 2008-03-10 16:58:52 +00:00
Scott Michel
bb8e8fca47 Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's 
return ValueType can depend its operands' ValueType.

This is a cosmetic change, no functionality impacted.

llvm-svn: 48145
 2008-03-10 15:42:14 +00:00
Nicolas Geoffray
e3381f0f1f Add description of individual bits in CR. This fix PR1765. 
llvm-svn: 48143
 2008-03-10 14:12:10 +00:00
Christopher Lamb
32e5ce3d96 Allow insert_subreg into implicit, target-specific values. 
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.

llvm-svn: 48130
 2008-03-10 06:12:08 +00:00
Dale Johannesen
e6b0009792 Increase ISD::ParamFlags to 64 bits. Increase the ByValSize 
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff.  Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and 
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)

llvm-svn: 48122
 2008-03-10 02:17:22 +00:00
Chris Lattner
4a5abdbe3f Darwin PPC64 indirect call target goes in X12, not R12. This fixes these 
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll

llvm-svn: 48120
 2008-03-09 20:49:33 +00:00
Chris Lattner
23ee644c71 cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking. 
llvm-svn: 48119
 2008-03-09 20:31:11 +00:00
Chris Lattner
9185c43c7d make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll 
llvm-svn: 48118
 2008-03-09 20:12:44 +00:00
Chris Lattner
b6bfedbcfd teach X86InstrInfo::copyRegToReg how to copy into ST(0) from 
an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.

llvm-svn: 48107
 2008-03-09 09:15:31 +00:00
Chris Lattner
b29a963cf5 add some code to support cross-register class copying from 
RST -> RFP{32/64/80}.  We only handle ST(0) for now.

llvm-svn: 48104
 2008-03-09 08:46:19 +00:00
Chris Lattner
53b86390b7 rearrange some code, no functionality change. 
llvm-svn: 48101
 2008-03-09 07:58:04 +00:00
Chris Lattner
71189e9501 claim ST(x) registers are 80 bits, which is true. This doesn't affect 
codegen yet because these can't be spilled (they don't exist until after RA).

llvm-svn: 48098
 2008-03-09 07:49:01 +00:00
Chris Lattner
2e7537b60b rename FP_SETRESULT -> FP_SET_ST0 
llvm-svn: 48094
 2008-03-09 07:08:44 +00:00
Chris Lattner
826402e365 rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for 
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.

llvm-svn: 48093
 2008-03-09 07:05:32 +00:00
Chris Lattner
b628208161 Finish implementing a readme entry: when inserting an i64 variable 
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle.  This allows us to compile
vec_set-B.ll into:

_test3:
	movl	$1234567, %eax
	andl	4(%esp), %eax
	movd	%eax, %xmm0
	ret

instead of:

_test3:
	subl	$28, %esp
	movl	$1234567, %eax
	andl	32(%esp), %eax
	movl	%eax, (%esp)
	movl	$0, 4(%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48090
 2008-03-09 05:42:06 +00:00
Chris Lattner
b741ebba29 add a note 
llvm-svn: 48064
 2008-03-09 01:08:22 +00:00
Chris Lattner
17f68a3075 Implement a readme entry, compiling 
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:
	movl	$1, %eax
	movd	%eax, %xmm0
	ret

instead of a constant pool load.

llvm-svn: 48063
 2008-03-09 01:05:04 +00:00
Chris Lattner
81deb3bc9c 1) Improve comments. 
2) Don't try to insert an i64 value into the low part of a 
   vector with movq on an x86-32 target.  This allows us to 
   compile:

__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:

_doload64:
	movaps	LCPI1_0, %xmm0
	ret

instead of:

_doload64:
	subl	$28, %esp
	movl	$0, 4(%esp)
	movl	$1, (%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48057
 2008-03-08 22:59:52 +00:00
Chris Lattner
405f2c6356 minor simplifications to this code, don't create a dead 
SCALAR_TO_VECTOR on paths that end up not using it.

llvm-svn: 48056
 2008-03-08 22:48:29 +00:00
Chris Lattner
ff9dc0af80 This one looks easy, add a note. 
llvm-svn: 48055
 2008-03-08 22:32:39 +00:00
Chris Lattner
b12697f8bb move these to the appropriate file 
llvm-svn: 48054
 2008-03-08 22:28:45 +00:00
Dale Johannesen
55d6e1a5aa More ppc32 byval handling (bug fixes). Things 
are looking pretty good now.

llvm-svn: 48043
 2008-03-08 01:41:42 +00:00
Evan Cheng
dba1dfe962 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. 
llvm-svn: 48042
 2008-03-08 00:58:38 +00:00
Dan Gohman
afeac8050d Add support for calls with i128 return values on ppc64. 
llvm-svn: 48041
 2008-03-08 00:19:12 +00:00
Bill Wendling
948c50e2be PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this 
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.

llvm-svn: 48030
 2008-03-07 20:49:02 +00:00
Dan Gohman
5bf464e1e6 Add support for lowering 128-bit shifts on ppc64. 
llvm-svn: 48029
 2008-03-07 20:36:53 +00:00
Dale Johannesen
3e6bacf7be Next bits of PPC byval handling. Basically functional 
but there are bugs.

llvm-svn: 48028
 2008-03-07 20:27:40 +00:00
Chris Lattner
08ec4919ea Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl). 
llvm-svn: 48027
 2008-03-07 20:18:24 +00:00
Chris Lattner
2f13ccc181 Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work 
with 32 or 64-bit operands/results.

llvm-svn: 48026
 2008-03-07 20:13:51 +00:00
Chris Lattner
aa81dc7d21 mark frem as expand for all legal fp types on x86, regardless of whether 
we're using SSE or not.  This fixes PR2122.

llvm-svn: 48006
 2008-03-07 06:36:32 +00:00
Gabor Greif
92e00c1e50 some more spelling changes 
llvm-svn: 47996
 2008-03-06 10:51:21 +00:00
Scott Michel
8dd2324903 Refine Cell's i64 constant generation code to cover more constants where the 
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)

llvm-svn: 47985
 2008-03-06 04:02:54 +00:00
Andrew Lenharth
0c26f5bb94 gcc likes things spelled correctly 
llvm-svn: 47981
 2008-03-05 23:41:37 +00:00
Dale Johannesen
6bcc9808db Next bit of PPC ByVal handling; call-site code seems 
correct now.

llvm-svn: 47978
 2008-03-05 23:31:27 +00:00
Scott Michel
c29399e54e - Fix support for "special" i64 immediates that can be loaded 
using IL, ILA, et. al. v2i64 and i64 are now supported by
  the select bits (SELB) instruction.

- Add missing comparison operations (testcase forthcoming)

- More multiclass refactoring.

llvm-svn: 47973
 2008-03-05 23:02:02 +00:00
Chris Lattner
83e0b885f8 evan implemented this. 
llvm-svn: 47948
 2008-03-05 17:11:51 +00:00
Evan Cheng
a36562006a isTwoAddress = 1 -> Constraints. 
llvm-svn: 47941
 2008-03-05 08:19:16 +00:00
Evan Cheng
6c2bb7c67e PSLLWri etc. are two-address instructions. 
llvm-svn: 47940
 2008-03-05 08:11:27 +00:00
Chris Lattner
7571a88209 add a note 
llvm-svn: 47939
 2008-03-05 07:22:39 +00:00
Evan Cheng
d421708e35 Ignore debugging related instructions if they get this far. 
llvm-svn: 47934
 2008-03-05 02:34:36 +00:00
Evan Cheng
a2939a16de Rather than asserting. Dump out the MI that we are not able to encode and abort. 
llvm-svn: 47933
 2008-03-05 02:08:03 +00:00
Evan Cheng
e0b3c221ab Add a target lowering hook to control whether it's worthwhile to compress fp constant. 
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.

llvm-svn: 47931
 2008-03-05 01:30:59 +00:00
Andrew Lenharth
95c88272c6 64bit CAS on 32bit x86. 
llvm-svn: 47929
 2008-03-05 01:15:49 +00:00
Evan Cheng
18064ddb5b Refactor code. Remove duplicated functions that basically do the same thing as 
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.

llvm-svn: 47927
 2008-03-05 00:59:57 +00:00
Bill Wendling
37f5b4586a Removed spurious EnablePPCRS check. 
llvm-svn: 47918
 2008-03-04 23:27:33 +00:00
Dale Johannesen
86867d323e Move PPC lowering functions into PPCTargetLowering 
class (cosmetic).  First piece of byval implementation;
this doesn't work yet.  No functional change.

llvm-svn: 47917
 2008-03-04 23:17:14 +00:00
Bill Wendling
dc9de245cb Use a command-line option to turn register scavenging on/off for PPC. 
llvm-svn: 47915
 2008-03-04 23:13:51 +00:00