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Commit Graph

60 Commits

Author SHA1 Message Date
Jack Carter
10d56b481a This patch that sets the Mips ELF header flag for
MicroMips architectures. 

Contributer: Zoran Jovanovic
 
llvm-svn: 174360
2013-02-05 09:30:03 +00:00
Jack Carter
3dfa61ae2c This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 
llvm-svn: 174358
2013-02-05 08:32:10 +00:00
Jack Carter
9054213d30 This patch implements runtime Mips specific
setting of ELF header e_flags.

Contributer: Jack Carter
 
llvm-svn: 173884
2013-01-30 02:16:36 +00:00
Jack Carter
26eec3af74 This patch implements parsing the .word
directive for the Mips assembler.

Contributer: Vladimir Medic
 
llvm-svn: 173407
2013-01-25 01:31:34 +00:00
Jack Carter
3f50a8d5c0 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Support for Mips register information sections.

Mips ELF object files have a section that is dedicated
to register use info. Some of this information such as
the assumed Global Pointer value is used by the linker
in relocation resolution.

The register info file is .reginfo in o32 and .MIPS.options
in 64 and n32 abi files.

This patch contains the changes needed to create the sections,
but leaves the actual register accounting for a future patch.


Contributer: Jack Carter
 
llvm-svn: 172847
2013-01-18 21:20:38 +00:00
Jack Carter
2737a54489 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

Removal of redundant code and formatting fixes.

Contributers: Jack Carter/Vladimir Medic
 
llvm-svn: 172842
2013-01-18 20:15:06 +00:00
Jack Carter
fc7b77744d This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172685
2013-01-17 00:28:20 +00:00
Jack Carter
6e4e11b877 reverting 172579
llvm-svn: 172594
2013-01-16 01:29:10 +00:00
Jack Carter
d951346d6e Akira,
Hope you are feeling better.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172579
2013-01-16 00:07:45 +00:00
Jack Carter
f7f756715f This patch fixes a Mips specific bug where
we need to generate a N64 compound relocation
R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE.

The bug was exposed by the SingleSourcetest case 
DuffsDevice.c.

Contributer: Jack Carter
llvm-svn: 172496
2013-01-15 01:08:02 +00:00
Jack Carter
d66ed8368e This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic
llvm-svn: 172284
2013-01-12 01:03:14 +00:00
Jack Carter
ac447a4205 This patch produces the correct addend value for
an R_MIPS_GPREL16 relocation.


Contributer: Jack Carter
llvm-svn: 171882
2013-01-08 19:01:28 +00:00
Jack Carter
f36167d718 This patch produces the correct pointer size
value in the 64 bit .eh_frame section.

It doesn't however allow exception handling to work
yet since it depends on the correct relocation model
being set in the ELF header flags.


Contributer: Jack Carter
llvm-svn: 171881
2013-01-08 18:53:20 +00:00
Akira Hatanaka
4b2123dd9c [mips] Fix encoding of BAL instruction. Also, fix assembler test case which
was not catching the error.

llvm-svn: 170953
2012-12-21 23:13:59 +00:00
Jack Carter
8fc37da48b Mips direct object xgot support
This patch provides support for the MIPS relocations:

    *)  R_MIPS_GOT_HI16
    *)  R_MIPS_GOT_LO16
    *)  R_MIPS_CALL_HI16
    *)  R_MIPS_CALL_LO16

These are used for large GOT instruction sequences.

Contributer: Jack Carter
llvm-svn: 168471
2012-11-21 23:38:59 +00:00
Akira Hatanaka
06b2c52edc [mips] Stop reserving register AT and use register scavenger when a scratch
register is needed.

llvm-svn: 167341
2012-11-03 00:05:43 +00:00
David Chisnall
16bdae8734 Add test cases for correct parsing of register names in 32- and 64-bit modes.
llvm-svn: 165713
2012-10-11 12:42:49 +00:00
David Chisnall
41ea5b7975 Expose move to/from coprocessor instructions in MIPS64 mode.
Note: [D]M{T,F}CP2 is just a recommended encoding.  Vendors often provide a
custom CP2 that interprets instructions differently and may wish to add their
own instructions that use this opcode.  We should ensure that this is easy to
do.  I will probably add a 'has custom CP{0-3}' subtarget flag to make this
easy: We want to avoid the GCC situation where every MIPS vendor makes a custom
fork that breaks every other MIPS CPU and so can't be merged upstream.

llvm-svn: 165711
2012-10-11 10:21:34 +00:00
Jack Carter
f403d95eb4 Initial assembler implementation of Mips load address macro
This patch provides initial implementation of load address 
macro instruction for Mips. We have implemented two kinds 
of expansions with their variations depending on the size 
of immediate operand:

 1) load address with immediate value directly:
    * la d,j => addiu d,$zero,j   (for -32768 <= j <= 65535)
    * la d,j => lui d,hi16(j)
                ori d,d,lo16(j)   (for any other 32 bit value of j)

 2) load load address with register offset value
    * la d,j(s) => addiu d,s,j     (for -32768 <= j <= 65535)
    * la d,j(s) => lui d,hi16(j)   (for any other 32 bit value of j)
                   ori d,d,lo16(j)
                   addu d,d,s

This patch does not cover the case when the address is loaded 
from the value of the label or function.

Contributer: Vladimir Medic
llvm-svn: 165561
2012-10-09 23:29:45 +00:00
Jack Carter
c5f946b170 Adding support for instructions mfc0, mfc2, mtc0, mtc2
move from and to coprocessors 0 and 2.

Contributer: Vladimir Medic
llvm-svn: 165351
2012-10-06 01:17:37 +00:00
Jack Carter
a6d222bf00 Implement methods that enable expansion of load immediate
macro instruction (li) in the assembler.

We have identified three possible expansions depending on 
the size of immediate operand:
  1) for 0 ≤ j ≤ 65535.
     li d,j =>
     ori d,$zero,j

  2) for −32768 ≤ j < 0.
     li d,j =>
     addiu d,$zero,j

  3) for any other value of j that is representable as a 32-bit integer.
     li d,j =>
     lui d,hi16(j)
     ori d,d,lo16(j)

All of the above have been implemented in ths patch.

Contributer: Vladimir Medic
llvm-svn: 165199
2012-10-04 04:03:53 +00:00
Jack Carter
f160360b70 This patch is a partial implementation of mips .set assembler directive. Directive is defined as follows:
.set option
The patch implements following options

    at - lets the assembler use the $at register for macros,
         but generates warnings if the source program uses $at

    noat - let source programs use $at without issuingwarnings.

    noreorder - prevents the assembler from reordering machine 
                language instructions.
    nomacro - causes the assembler to print a warning whenever 
              an assembler operation generates more than one 
              machine language instruction.
    macro - lets the assembler generate multiple machine instructions 
            from a single assembler instruction
    reorder - lets the assembler reorder machine language 
               instructions to improve performance

The above variants are parsed and their boolean values set or unset.
The code to actually use them will come later.

Following options are not implemented yet:

nomips16
nomicromips
move
nomove

Contributer: Vladimir Medic
llvm-svn: 165194
2012-10-04 02:29:46 +00:00
Jack Carter
775e191ae5 Initial relocations test for the Mips standalone assembler.
This is not an exhaustive set, but something we can build on.

Contributer: Vladimir Medic
llvm-svn: 163419
2012-09-07 20:38:18 +00:00
Jack Carter
93a95cbdde The Mips standalone assembler aliased instruction support.
The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.

These changes are in the instruction td file.

Test cases included

Contributer: Vladimir Medic
llvm-svn: 163368
2012-09-07 01:42:38 +00:00
Jack Carter
d4ab2f65df The Mips standalone assembler intial directive support.
Actually these are just stubs for parsing the directives.
Semantic support will come later.

Test cases included

Contributer: Vladimir Medic
llvm-svn: 163364
2012-09-07 00:48:02 +00:00
Jack Carter
0a824e63ab The Mips standalone assembler fpu instruction support.
Test cases included

Contributer: Vladimir Medic
llvm-svn: 163363
2012-09-07 00:23:42 +00:00
Jack Carter
b3ec1ea360 The Mips standalone assembler memory instruction support.
This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw

Test case included

Contributer: Vladimir Medic
llvm-svn: 163346
2012-09-06 20:00:02 +00:00
Jack Carter
2a8cbd60d3 Mips specific llvm assembler support for branch and jump instructions.
Test case included.

Contributer: Vladimir Medic
llvm-svn: 163277
2012-09-06 00:43:26 +00:00
Jack Carter
f7221de872 Mips specific llvm assembler support for ALU instructions. This includes
register support. Test case included.

Contributer: Vladimir Medic
llvm-svn: 163268
2012-09-05 23:34:03 +00:00
Jack Carter
a986033975 The instruction DINS may be transformed into DINSU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword

llvm-svn: 163010
2012-08-31 18:06:48 +00:00
Jack Carter
c918c7a81f The instruction DEXT may be transformed into DEXTU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword

llvm-svn: 162782
2012-08-28 20:07:41 +00:00
Jack Carter
a525a54e64 Some instructions are passed to the assembler to be
transformed to the final instruction variant. An
example would be dsrll which is transformed into 
dsll32 if the shift value is greater than 32.

For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.

llvm-svn: 162779
2012-08-28 19:07:39 +00:00
Akira Hatanaka
ab45f57419 Fix mips' long branch pass.
Instructions emitted to compute branch offsets now use immediate operands
instead of symbolic labels. This change was needed because there were problems
when R_MIPS_HI16/LO16 relocations were used to make shared objects.

llvm-svn: 162731
2012-08-28 03:03:05 +00:00
Akira Hatanaka
0602c4e928 Add option disable-mips-delay-filler. Turn on mips' delay slot filler by
default.

Patch by Carl Norum.

llvm-svn: 162339
2012-08-22 02:51:28 +00:00
Jack Carter
1b099ac7c7 For mips64 switch statements in subroutines could generate
within the codegen EK_GPRel64BlockAddress. This was not 
supported for direct object output and resulted in an assertion.

This change adds support for EK_GPRel64BlockAddress for 
direct object.

One fallout from this is to turn on rela relocations 
for mips64 to match gas.

llvm-svn: 162334
2012-08-22 00:49:30 +00:00
Jack Carter
5ce6f4b4e5 Another 32 to 64 bit sign extension bug.
The fields in the td definition were switched.

llvm-svn: 161607
2012-08-09 19:43:18 +00:00
Jack Carter
32420dd092 The define for 64 bit sign extension neglected to
initialize fields of the class that it used.

The result was nonsense code.

Before:
0000000000000000 <foo>:
   0:    00441100     0x441100
   4:    03e00008     jr    ra
   8:    00000000     nop

After:
0000000000000000 <foo>:
   0:    00041000     sll    v0,a0,0x0
   4:    03e00008     jr    ra
   8:    00000000     nop 

llvm-svn: 161377
2012-08-07 00:35:22 +00:00
Jack Carter
3f30c3effe The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64
were using a class defined for 32 bit instructions and 
thus the instruction was for addiu instead of daddiu.

This was corrected by adding the instruction opcode as a 
field in the  base class to be filled in by the defs.

llvm-svn: 161359
2012-08-06 23:29:06 +00:00
Jack Carter
fdb00bef02 Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.
These 2 relocations gain access to the 
highest and the second highest 16 bits
of a 64 bit object.

R_MIPS_HIGHER %higher(A+S)
The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. 

R_MIPS_HIGHEST %highest(A+S)
The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. 

llvm-svn: 161348
2012-08-06 21:26:03 +00:00
Jack Carter
f2bf098c4f Doubleword Shift Left Logical Plus 32
Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63

Here is a description of DSLL:

Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits

Description: GPR[rd] <- GPR[rt] << (sa+32)

The 64-bit doubleword contents of GPR rt are shifted left, inserting
 zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.

This patch implements the direct object output of these instructions.

llvm-svn: 160277
2012-07-16 15:14:51 +00:00
Jack Carter
b8e3cf5fbc The Mips specific relocation R_MIPS_GOT_DISP
is used in cases where global symbols are 
directly represented in the GOT and we use an 
offset into the global offset table.

This patch adds direct object support for R_MIPS_GOT_DISP.

llvm-svn: 160183
2012-07-13 19:15:47 +00:00
Jack Carter
d4d064d1da test case for revision 160084: Alignment filling between Mips function units
llvm-svn: 160177
2012-07-13 18:14:01 +00:00
Jack Carter
4355dfdc86 Pass the correct ELFOSABI enumeration to the MipsELFObjectWriter constructor
Contributer: Sasa Stankovic 
llvm-svn: 159574
2012-07-02 20:04:43 +00:00
Jack Carter
156781dada This allows hello world to be compiled for Mips 64 direct object.
It takes advantage of r159299 which introduces relocation support for N64. 
elf-dump needed to be upgraded to support N64 relocations as well.

This passes make check.

Jack

llvm-svn: 159302
2012-06-27 23:13:42 +00:00
Meador Inge
b8cf9886db PR13013: ELF Type identification fails for MSB type ELF files.
Fix 'sys::IdentifyFileType' to work with big and little endian byte orderings
when reading the ELF object file type.

Initial patch by Stefan Hepp.

llvm-svn: 159138
2012-06-25 14:48:43 +00:00
Akira Hatanaka
431ee824c6 Make the following changes in MipsAsmPrinter.cpp:
- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.

llvm-svn: 156689
2012-05-12 00:48:43 +00:00
Akira Hatanaka
bc52a1662b Insert instructions to the entry basic block which initializes the global
pointer register. 


This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:

- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
  allocator decide which register to assign to it or whether spill/reloads are
  needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
  for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.

llvm-svn: 156671
2012-05-12 00:17:17 +00:00
Akira Hatanaka
04dee7c9fc This patch fixes 3 problems:
1. CHECKNEXT was used instead of CHECK-NEXT which caused the line to be
   ignored which in turn hid the next 2 problems:
2. ('sh_offset', 0x{{{[0-9,a-f]+}}) had one too many leading curly braces and
   failed to do it's job of accepting all hex digits and:
3. The check for the hex values for the code instructions didn't account for
   blank separators.

Patch by Jack Carter. 

llvm-svn: 154842
2012-04-16 18:20:26 +00:00
Akira Hatanaka
0f31530336 Do not add offset in applyFixup. This has already been accounted for in Value.
llvm-svn: 154838
2012-04-16 18:00:19 +00:00
Akira Hatanaka
f37a1c4323 Initial 64 bit direct object support.
This patch allows llvm to recognize that a 64 bit object file is being produced
and that the subsequently generated ELF header has the correct information.

The test case checks for both big and little endian flavors.

Patch by Jack Carter.

llvm-svn: 153889
2012-04-02 19:25:22 +00:00