1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-30 15:32:52 +01:00
Commit Graph

2295 Commits

Author SHA1 Message Date
Eli Bendersky
4236f7b1ee Add the align_to_end option to .bundle_lock in the MC implementation of aligned
bundling. The document describing this feature and the implementation has also
been updated:

https://sites.google.com/a/chromium.org/dev/nativeclient/pnacl/aligned-bundling-support-in-llvm

llvm-svn: 171797
2013-01-07 21:51:08 +00:00
Craig Topper
7af95b6c84 Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.

Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.

llvm-svn: 171668
2013-01-06 20:39:29 +00:00
Adhemerval Zanella
fb3cdfff15 PowerPC: Fix eh_frame relocation for PIC
This patch fixes the PPC eh_frame definitions for the personality and 
frame unwinding for PIC objects. It makes PIC build correctly creates
relative relocations in the '.rela.eh_frame' segments and thus avoiding
a text relocation that generates a DT_TEXTREL segments in link phase.

llvm-svn: 171506
2013-01-04 19:08:13 +00:00
Kevin Enderby
255beae3d9 Adds missing aliases for fcom and fcomp instructions without arguments.
Patch by Michael M Kuperstein!

llvm-svn: 171414
2013-01-02 21:20:15 +00:00
Akira Hatanaka
4b2123dd9c [mips] Fix encoding of BAL instruction. Also, fix assembler test case which
was not catching the error.

llvm-svn: 170953
2012-12-21 23:13:59 +00:00
Eli Bendersky
50e22a71d4 Change Lit error redirection to FileCheck to a more common syntax since it
can potentially cause some bots to fail.

llvm-svn: 170726
2012-12-20 19:54:02 +00:00
Eli Bendersky
5420e6ae4a Add a largish auto-generated test for the aligned bundling feature, along with
the script generating it. The test should never be modified manually. If anyone
needs to change it, please change the script and re-run it.

The script is placed into utils/testgen - I couldn't think of a better place,
and after some discussion on IRC this looked like a logical location.

llvm-svn: 170720
2012-12-20 19:16:57 +00:00
Eli Bendersky
49e8321d21 Tests for the aligned bundling support added in r170718
llvm-svn: 170719
2012-12-20 19:07:30 +00:00
Roman Divacky
7a967134bc Remove edis - the enhanced disassembler. Fixes PR14654.
llvm-svn: 170578
2012-12-19 19:55:47 +00:00
NAKAMURA Takumi
3580df55e9 llvm/test/MC/ELF/comp-dir.s: Appease MSYS Bash.
llvm-svn: 170410
2012-12-18 05:08:12 +00:00
Chandler Carruth
58c5f67a85 Add a triple to this test -- it has to be an ELF platform...
llvm-svn: 170374
2012-12-17 21:44:50 +00:00
Chandler Carruth
fcc965daa6 Prepare LLVM to fix PR14625, exposing a hook in MCContext to manage the
compilation directory.

This defaults to the current working directory, just as it always has,
but now an assembler can choose to override it with a custom directory.
I've taught llvm-mc about this option and added a test case.

llvm-svn: 170371
2012-12-17 21:32:42 +00:00
Richard Osborne
efed5dbcc7 Add instruction encodings / disassembly support for l2r instructions.
llvm-svn: 170345
2012-12-17 16:28:02 +00:00
Richard Osborne
b4aaa991f6 Add instruction encodings for PEEK and ENDIN.
Previously these were marked with the wrong format.

llvm-svn: 170334
2012-12-17 14:23:54 +00:00
Richard Osborne
c66ab02537 Add instruction encodings / disassembly support for rus instructions.
llvm-svn: 170330
2012-12-17 13:50:04 +00:00
Richard Osborne
92f0d25122 Add instruction encodings for ZEXT and SEXT.
Previously these were marked with the wrong format.

llvm-svn: 170327
2012-12-17 13:20:37 +00:00
Richard Osborne
cccafe2726 Add instruction encodings / disassembly support for 2r instructions.
llvm-svn: 170323
2012-12-17 12:29:31 +00:00
Richard Osborne
815fca9724 Add instruction encodings / disassembly support for 0r instructions.
llvm-svn: 170322
2012-12-17 12:26:29 +00:00
Richard Osborne
91f0d743ac Add tests for disassembly of 1r XCore instructions.
llvm-svn: 170295
2012-12-16 18:06:30 +00:00
Kevin Enderby
d775b42d99 Make sure the alternate PC+imm syntax of LDR instruction with a small
immediate generates the narrow version.  Needed when doing round-trip
assemble/disassemble testing using the alternate syntax that specifies
'pc' directly.

llvm-svn: 170255
2012-12-14 23:04:25 +00:00
Eli Bendersky
462f346f2c Make this Lit config file a bit slimmer
llvm-svn: 170083
2012-12-13 02:03:46 +00:00
Hao Liu
e24e94d1cb revert the test change
llvm-svn: 169823
2012-12-11 06:25:18 +00:00
Hao Liu
a4b44869a6 A newbie try a test commit
llvm-svn: 169821
2012-12-11 06:22:54 +00:00
Eli Bendersky
139a219553 Add a test for explicitly exercising the mc-relax-all flag.
llvm-svn: 169764
2012-12-10 20:36:01 +00:00
Eli Bendersky
58ccdb5e69 Add separate statistics for Data and Inst fragments emitted during relaxation.
Also fixes a test that was overly-sensitive to the exact order of statistics
emitted.

llvm-svn: 169619
2012-12-07 17:59:21 +00:00
Tim Northover
2dbbd221f7 Added Mapping Symbols for ARM ELF
Before this patch, when you objdump an LLVM-compiled file, objdump tried to
decode data-in-code sections as if they were code.  This patch adds the missing
Mapping Symbols, as defined by "ELF for the ARM Architecture" (ARM IHI 0044D).

Patch based on work by Greg Fitzgerald.

llvm-svn: 169609
2012-12-07 16:50:23 +00:00
David Sehr
f67cd34524 Correct ARM NOP encoding
The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which
causes the emission of a coprocessor instruction rather than "mov r0, r0"
as indicated in the comment.  The test also checks for the wrong encoding.

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html

llvm-svn: 169420
2012-12-05 21:01:27 +00:00
David Sehr
fb2c0537ee Test commit.
llvm-svn: 169410
2012-12-05 19:47:56 +00:00
Kevin Enderby
94941df94f Added a option to the disassembler to print immediates as hex.
This is for the lldb team so most of but not all of the values are
to be printed as hex with this option.  Some small values like the
scale in an X86 address were requested to printed in decimal
without the leading 0x.

There may be some tweaks need to places that may still be in
decimal that they want in hex.  Specially for arm.  I made my best
guess.  Any tweaks from here should be simple.

I also did the best I know now with help from the C++ gurus
creating the cleanest formatImm() utility function and containing
the changes.  But if someone has a better idea to make something
cleaner I'm all ears and game for changing the implementation.

rdar://8109283

llvm-svn: 169393
2012-12-05 18:13:19 +00:00
Eli Bendersky
12bb44ebf1 A test in thid directory was not being run because lit.local.cfg didn't
include .ll files. Fix that.

llvm-svn: 169283
2012-12-04 17:00:11 +00:00
Kevin Enderby
d3ba5ff018 Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst
which would then cause an assert when printed.  rdar://11437956

llvm-svn: 168960
2012-11-29 23:47:11 +00:00
Ulrich Weigand
3ab1bb1fd8 Fix initial frame state on powerpc64.
The createPPCMCAsmInfo routine used PPC::R1 as the initial frame
pointer register, but on PPC64 the 32-bit R1 register does not
have a corresponding DWARF number, causing invalid CIE initial
frame state to be emitted.  Fix by using PPC::X1 instead.

llvm-svn: 168799
2012-11-28 18:21:03 +00:00
Eric Christopher
178793931e The section is .debug_line.
llvm-svn: 168666
2012-11-27 01:40:36 +00:00
Eli Bendersky
e5d04ab064 Make this test less sensitive.
It currently assumes register numbering and any harmless change in the X86
register naming makes it fail. It's enough to match the register names.

llvm-svn: 168632
2012-11-26 23:27:09 +00:00
Rafael Espindola
81ee486113 Add support for .cfi_register now that it is easy to extent the representation
to support it. Original patch with the parsing and plumbing by the PaX team and
Roman Divacky. I added the bits in MCDwarf.cpp and the test.

llvm-svn: 168565
2012-11-25 15:14:49 +00:00
Rafael Espindola
a6e1d5393f Implement .cfi_undefined. Based on a patch from PaX team, updated by
Roman Divacky. I just added the testcase.

llvm-svn: 168520
2012-11-23 16:59:41 +00:00
Jack Carter
8fc37da48b Mips direct object xgot support
This patch provides support for the MIPS relocations:

    *)  R_MIPS_GOT_HI16
    *)  R_MIPS_GOT_LO16
    *)  R_MIPS_CALL_HI16
    *)  R_MIPS_CALL_LO16

These are used for large GOT instruction sequences.

Contributer: Jack Carter
llvm-svn: 168471
2012-11-21 23:38:59 +00:00
Bill Schmidt
f294eb980a This patch is in preparation for adding medium code model support to the
PPC64 target.  The five tests modified herein test code generation that is
sensitive to the code model selected.  So I've added -code-model=small to
the RUN commands for each.

Since small code model is the default, this has no effect for now; but this
prepares us for eventually changing the default to medium code model for PPC64.

Test changes verified with small and medium code model as default on
powerpc64-unknown-linux-gnu.  All tests continue to pass.

llvm-svn: 167999
2012-11-14 23:23:27 +00:00
Jakub Staszak
14a889a054 Remove DOS line endings.
llvm-svn: 167968
2012-11-14 20:18:34 +00:00
Jim Grosbach
2742e92ea2 X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.
When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.

rdar://12700702

llvm-svn: 167937
2012-11-14 18:04:47 +00:00
Alexey Samsonov
92705fb808 Emit relocations from .debug_aranges to .debug_info for asm files
llvm-svn: 167926
2012-11-14 09:55:38 +00:00
Michael J. Spencer
b158d9cd2a [MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!
llvm-svn: 167877
2012-11-13 22:04:09 +00:00
Ulrich Weigand
7e5e3a1ed0 Add test case to verify correct relocs being generated for
TLS symbols on PowerPC using the integrated assembler.

llvm-svn: 167875
2012-11-13 21:53:43 +00:00
Evan Cheng
2599006e46 Convert an improper CodeGen test to a MC test.
llvm-svn: 167663
2012-11-10 04:30:40 +00:00
Michael Liao
59114df23b Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region

llvm-svn: 167573
2012-11-08 07:28:54 +00:00
Kevin Enderby
d988c6daf6 Fix for PR14264 cause by commit r167237 which did not take into account a
possible buffer change with a .macro directive.

rdar://12637628

llvm-svn: 167408
2012-11-05 21:55:41 +00:00
Akira Hatanaka
06b2c52edc [mips] Stop reserving register AT and use register scavenger when a scratch
register is needed.

llvm-svn: 167341
2012-11-03 00:05:43 +00:00
Akira Hatanaka
109078895c [mips] Fix disassembler test cases.
llvm-svn: 167326
2012-11-02 22:20:10 +00:00
Kevin Enderby
efec4e2817 Add support for generating dwarf debugging info with assembly files
run through the 'C' preprocessor.  That is pick up the file name
and line numbers from the cpp hash file line comments for the
dwarf file and line numbers tables.

rdar://9275556

llvm-svn: 167237
2012-11-01 17:31:35 +00:00
Jim Grosbach
ca24351f26 MC: Simple example parser for MC assembly markup.
Nothing fancy, just a simple demonstration parser.

llvm-svn: 167181
2012-10-31 23:24:13 +00:00
Jim Grosbach
6585037b8c ARM: Better disassembly for pc-relative LDR.
When the operand is a plain immediate rather than a label, print it
as [pc, #imm] like we do for the Thumb2 wide encoding variant.

rdar://12154503

llvm-svn: 166991
2012-10-30 01:04:51 +00:00
Kevin Enderby
ecb9e2620c Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. 

llvm-svn: 166982
2012-10-29 23:27:20 +00:00
Chad Rosier
651ecf255c [ms-inline asm] Add support for the [] operator. Essentially, [expr1][expr2] is
equivalent to [expr1 + expr2].  See test cases for more examples.
rdar://12470392

llvm-svn: 166949
2012-10-29 18:01:54 +00:00
Adhemerval Zanella
b08709a59f Initial TOC support for PowerPC64 object creation
This patch adds initial PPC64 TOC MC object creation using the small mcmodel
(a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC,
R_PPC64_TOC16, and R_PPC64_TOC16DS).

The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter'
is meant to avoid the creation of an unreferenced ".TOC." symbol (used in
the .odp creation) as well to set the R_PPC64_TOC relocation target as the
temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should
not point to any symbol.

llvm-svn: 166677
2012-10-25 12:27:42 +00:00
Chad Rosier
3935e5ec30 Tell llvm-mc we're using intel syntax, so we don't have to use directives.
llvm-svn: 166640
2012-10-24 23:34:38 +00:00
Chad Rosier
492e58a0f7 [ms-inline asm] Add back-end test case for r166632. Make sure we emit the
correct .s output as well as get the correct encoding by the integrated
assembler.

llvm-svn: 166638
2012-10-24 23:10:28 +00:00
Kevin Enderby
0f6b703b72 Add support for annotated disassembly output for X86 and arm.
Per the October 12, 2012 Proposal for annotated disassembly output sent out by
Jim Grosbach this set of changes implements this for X86 and arm.  The llvm-mc
tool now has a -mdis option to produced the marked up disassembly and a couple
of small example test cases have been added.

rdar://11764962

llvm-svn: 166445
2012-10-22 22:31:46 +00:00
Benjamin Kramer
1d2b1ffd35 X86: Depending on the local semantics of .align this test can also emit a nopl instead of nopw.
llvm-svn: 165880
2012-10-13 17:38:00 +00:00
Benjamin Kramer
80915069f7 X86: Disable long nops for all cpus prior to pentiumpro/i686.
llvm-svn: 165878
2012-10-13 17:28:35 +00:00
David Chisnall
16bdae8734 Add test cases for correct parsing of register names in 32- and 64-bit modes.
llvm-svn: 165713
2012-10-11 12:42:49 +00:00
David Chisnall
41ea5b7975 Expose move to/from coprocessor instructions in MIPS64 mode.
Note: [D]M{T,F}CP2 is just a recommended encoding.  Vendors often provide a
custom CP2 that interprets instructions differently and may wish to add their
own instructions that use this opcode.  We should ensure that this is easy to
do.  I will probably add a 'has custom CP{0-3}' subtarget flag to make this
easy: We want to avoid the GCC situation where every MIPS vendor makes a custom
fork that breaks every other MIPS CPU and so can't be merged upstream.

llvm-svn: 165711
2012-10-11 10:21:34 +00:00
Craig Topper
96909f4ec9 Test case for r165480.
llvm-svn: 165594
2012-10-10 02:54:23 +00:00
Jack Carter
f403d95eb4 Initial assembler implementation of Mips load address macro
This patch provides initial implementation of load address 
macro instruction for Mips. We have implemented two kinds 
of expansions with their variations depending on the size 
of immediate operand:

 1) load address with immediate value directly:
    * la d,j => addiu d,$zero,j   (for -32768 <= j <= 65535)
    * la d,j => lui d,hi16(j)
                ori d,d,lo16(j)   (for any other 32 bit value of j)

 2) load load address with register offset value
    * la d,j(s) => addiu d,s,j     (for -32768 <= j <= 65535)
    * la d,j(s) => lui d,hi16(j)   (for any other 32 bit value of j)
                   ori d,d,lo16(j)
                   addu d,d,s

This patch does not cover the case when the address is loaded 
from the value of the label or function.

Contributer: Vladimir Medic
llvm-svn: 165561
2012-10-09 23:29:45 +00:00
Jack Carter
c5f946b170 Adding support for instructions mfc0, mfc2, mtc0, mtc2
move from and to coprocessors 0 and 2.

Contributer: Vladimir Medic
llvm-svn: 165351
2012-10-06 01:17:37 +00:00
Jack Carter
a6d222bf00 Implement methods that enable expansion of load immediate
macro instruction (li) in the assembler.

We have identified three possible expansions depending on 
the size of immediate operand:
  1) for 0 ≤ j ≤ 65535.
     li d,j =>
     ori d,$zero,j

  2) for −32768 ≤ j < 0.
     li d,j =>
     addiu d,$zero,j

  3) for any other value of j that is representable as a 32-bit integer.
     li d,j =>
     lui d,hi16(j)
     ori d,d,lo16(j)

All of the above have been implemented in ths patch.

Contributer: Vladimir Medic
llvm-svn: 165199
2012-10-04 04:03:53 +00:00
Jack Carter
f160360b70 This patch is a partial implementation of mips .set assembler directive. Directive is defined as follows:
.set option
The patch implements following options

    at - lets the assembler use the $at register for macros,
         but generates warnings if the source program uses $at

    noat - let source programs use $at without issuingwarnings.

    noreorder - prevents the assembler from reordering machine 
                language instructions.
    nomacro - causes the assembler to print a warning whenever 
              an assembler operation generates more than one 
              machine language instruction.
    macro - lets the assembler generate multiple machine instructions 
            from a single assembler instruction
    reorder - lets the assembler reorder machine language 
               instructions to improve performance

The above variants are parsed and their boolean values set or unset.
The code to actually use them will come later.

Following options are not implemented yet:

nomips16
nomicromips
move
nomove

Contributer: Vladimir Medic
llvm-svn: 165194
2012-10-04 02:29:46 +00:00
Jim Grosbach
037348ce80 MachO: direct-to-object attribute for data-in-code markers.
The target backend can support data-in-code load commands even when
the assembler doesn't, or vice-versa. Allow targets to opt-in for
direct-to-object.

PR13973.

llvm-svn: 164974
2012-10-01 22:20:54 +00:00
Jim Grosbach
22a8871d1f X86_32: Large Symbol+Offset relocations.
If the offset is more than 24-bits, it won't fit in a scattered
relocation offset field, so we fall back to using a non-scattered
relocation.

rdar://12358909

llvm-svn: 164724
2012-09-26 21:27:45 +00:00
Jim Grosbach
97e019d375 ARM: Darwin BL/BLX relocations to out-of-range symbols.
When a BL/BLX references a symbol in the same translation unit that is
out of range, use an external relocation. The linker will use this to
generate a branch island rather than a direct reference, allowing the
relocation to resolve correctly.

rdar://12359919

llvm-svn: 164615
2012-09-25 18:07:17 +00:00
Jim Grosbach
d5ba471995 ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.
rdar://9795790

llvm-svn: 164577
2012-09-25 00:08:13 +00:00
Anton Korobeynikov
0457dce9c9 Emit dtors into proper section while compiling in vcpp-compatible mode.
Patch by Kai!

llvm-svn: 164476
2012-09-23 15:53:47 +00:00
Tim Northover
7cab153d37 Fix edge cases of ARM shift operands in arith instructions.
As before with load instructions, oddities like "asr #32", "rrx" could
be printed incorrectly.

Patch by Chris Lidbury.

llvm-svn: 164456
2012-09-22 11:18:19 +00:00
Tim Northover
1c60305666 Fix the handling of edge cases in ARM shifted operands.
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

llvm-svn: 164455
2012-09-22 11:18:12 +00:00
Preston Gurd
79d6f55f89 Add support for macro parameters/arguments delimited by spaces,
to improve compatibility with GNU as.

Based on a patch by PaX Team.

Fixed assertion failures on non-Darwin and added additional test cases.

llvm-svn: 164248
2012-09-19 20:36:12 +00:00
Preston Gurd
ba1ce20a7b Support default parameters/arguments for assembler macros.
This patch is based on the one by PaX Team.

Patch by Andy Zhang!

llvm-svn: 164246
2012-09-19 20:29:04 +00:00
Preston Gurd
033b204a1f Enhance unmatched '.endr' directive error message in assembler.
The directive can be matched with directives other than '.rept'

Patch by Andy Zhang!

llvm-svn: 164245
2012-09-19 20:23:43 +00:00
NAKAMURA Takumi
12cdeb840a llvm/test/MC/X86/x86_nop.s: Make sure -arch=x86 when -mcpu=geode.
-mcpu doesn't infer -arch. Consider non-x86 host.

llvm-svn: 164185
2012-09-19 00:56:20 +00:00
Roman Divacky
30a607bf14 Add test for r164132.
llvm-svn: 164134
2012-09-18 16:19:10 +00:00
Jim Grosbach
7cb6ddb81b Assembler: Darwin variables defined via .set are no-dead-strip.
For gas compatibility.

rdar://12219394

llvm-svn: 163854
2012-09-13 23:11:31 +00:00
Chad Rosier
f7b609f0fb Add newline.
llvm-svn: 163565
2012-09-10 23:09:27 +00:00
Chad Rosier
e1355ead98 [ms-inline asm] Add support for .att_syntax directive.
llvm-svn: 163542
2012-09-10 20:54:39 +00:00
Benjamin Kramer
f7e00de5d0 Fix alignment of .comm and .lcomm on mingw32.
For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't
use the same setting for both. Fix this by reintroducing the LCOMM enum.
I verified this against mingw's gcc.

llvm-svn: 163420
2012-09-07 21:08:01 +00:00
Jack Carter
775e191ae5 Initial relocations test for the Mips standalone assembler.
This is not an exhaustive set, but something we can build on.

Contributer: Vladimir Medic
llvm-svn: 163419
2012-09-07 20:38:18 +00:00
Benjamin Kramer
f7fdee3ce3 MC: Overhaul handling of .lcomm
- Darwin lied about not supporting .lcomm and turned it into zerofill in the
  asm parser. Push the zerofill-conversion down into macho-specific code.
- This makes the tri-state LCOMMType enum superfluous, there are no targets
  without .lcomm.
- Do proper error reporting when trying to use .lcomm with alignment on a target
  that doesn't support it.
- .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2.
- Fixes PR13755 (.lcomm crashes on ELF).

llvm-svn: 163395
2012-09-07 17:25:13 +00:00
Benjamin Kramer
2c1f1b0513 PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for registers.
gas accepts this and it seems to be common enough to be worth supporting. This
doesn't affect the parsing of reg operands outside of .cfi directives.

llvm-svn: 163390
2012-09-07 14:51:35 +00:00
Jack Carter
93a95cbdde The Mips standalone assembler aliased instruction support.
The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.

These changes are in the instruction td file.

Test cases included

Contributer: Vladimir Medic
llvm-svn: 163368
2012-09-07 01:42:38 +00:00
Jack Carter
d4ab2f65df The Mips standalone assembler intial directive support.
Actually these are just stubs for parsing the directives.
Semantic support will come later.

Test cases included

Contributer: Vladimir Medic
llvm-svn: 163364
2012-09-07 00:48:02 +00:00
Jack Carter
0a824e63ab The Mips standalone assembler fpu instruction support.
Test cases included

Contributer: Vladimir Medic
llvm-svn: 163363
2012-09-07 00:23:42 +00:00
Jack Carter
b3ec1ea360 The Mips standalone assembler memory instruction support.
This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw

Test case included

Contributer: Vladimir Medic
llvm-svn: 163346
2012-09-06 20:00:02 +00:00
Tim Northover
bfaeb1ab9d Diagnose invalid alignments on duplicating VLDn instructions.
Patch by Chris Lidbury.

llvm-svn: 163323
2012-09-06 15:27:12 +00:00
Tim Northover
b12fa01bc6 Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.
Patch by Chris Lidbury.

llvm-svn: 163321
2012-09-06 15:17:49 +00:00
Tim Northover
1c637c210f Use correct part of complex operand to encode VST1 alignment.
Patch by Chris Lidbury.

llvm-svn: 163318
2012-09-06 14:36:55 +00:00
Jack Carter
2a8cbd60d3 Mips specific llvm assembler support for branch and jump instructions.
Test case included.

Contributer: Vladimir Medic
llvm-svn: 163277
2012-09-06 00:43:26 +00:00
Jack Carter
f7221de872 Mips specific llvm assembler support for ALU instructions. This includes
register support. Test case included.

Contributer: Vladimir Medic
llvm-svn: 163268
2012-09-05 23:34:03 +00:00
Jack Carter
a986033975 The instruction DINS may be transformed into DINSU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword

llvm-svn: 163010
2012-08-31 18:06:48 +00:00
Jim Grosbach
6d3cb70105 X86: Fix encoding of 'movd %xmm0, %rax'
The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v'
prefix, resulting in mis-assembly of the vanilla movd instruction.

llvm-svn: 162963
2012-08-31 00:30:30 +00:00
Jack Carter
c918c7a81f The instruction DEXT may be transformed into DEXTU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword

llvm-svn: 162782
2012-08-28 20:07:41 +00:00
Jack Carter
a525a54e64 Some instructions are passed to the assembler to be
transformed to the final instruction variant. An
example would be dsrll which is transformed into 
dsll32 if the shift value is greater than 32.

For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.

llvm-svn: 162779
2012-08-28 19:07:39 +00:00
Akira Hatanaka
ab45f57419 Fix mips' long branch pass.
Instructions emitted to compute branch offsets now use immediate operands
instead of symbolic labels. This change was needed because there were problems
when R_MIPS_HI16/LO16 relocations were used to make shared objects.

llvm-svn: 162731
2012-08-28 03:03:05 +00:00
Akira Hatanaka
0602c4e928 Add option disable-mips-delay-filler. Turn on mips' delay slot filler by
default.

Patch by Carl Norum.

llvm-svn: 162339
2012-08-22 02:51:28 +00:00