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Commit Graph

2295 Commits

Author SHA1 Message Date
Jack Carter
10d56b481a This patch that sets the Mips ELF header flag for
MicroMips architectures. 

Contributer: Zoran Jovanovic
 
llvm-svn: 174360
2013-02-05 09:30:03 +00:00
Jack Carter
3dfa61ae2c This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 
llvm-svn: 174358
2013-02-05 08:32:10 +00:00
Tim Northover
62526ce9c9 Add explicit triples to AArch64 tests
Only Linux is supported at the moment, and other platforms quickly fault. As a
result these tests would fail on non-Linux hosts. It may be worth making the
tests more generic again as more platforms are supported.

llvm-svn: 174170
2013-02-01 11:40:47 +00:00
Derek Schuff
ef8694af28 [MC] bundle alignment: prevent padding instructions from crossing bundle boundaries
llvm-svn: 174067
2013-01-31 17:00:03 +00:00
Tim Northover
e2b0519ed8 Add AArch64 as an experimental target.
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.

This initial commit should have support for:
    + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
      (except the late addition CRC instructions).
    + CodeGen features required for C++03 and C99.
    + Compilation for the "small" memory model: code+static data <
      4GB.
    + Absolute and position-independent code.
    + GNU-style (i.e. "__thread") TLS.
    + Debugging information.

The principal omission, currently, is performance tuning.

This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.

Further reviews would be gratefully received.

llvm-svn: 174054
2013-01-31 12:12:40 +00:00
Eli Bendersky
54b69d95ac Add a special ARM trap encoding for NaCl.
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html

Patch by JF Bastien

llvm-svn: 173943
2013-01-30 16:30:19 +00:00
Jack Carter
7c25c2553c This patch implements runtime ARM specific
setting of ELF header e_flags.

Contributer: Jack Carter
 
llvm-svn: 173885
2013-01-30 02:24:33 +00:00
Jack Carter
9054213d30 This patch implements runtime Mips specific
setting of ELF header e_flags.

Contributer: Jack Carter
 
llvm-svn: 173884
2013-01-30 02:16:36 +00:00
Jack Carter
7cd7b1f749 This patch reworks how llvm targets set
and update ELF header e_flags.

Currently gathering information such as symbol, 
section and data is done by collecting it in an 
MCAssembler object. From MCAssembler and MCAsmLayout 
objects ELFObjectWriter::WriteObject() forms and 
streams out the ELF object file.

This patch just adds a few members to the MCAssember 
class to store and access the e_flag settings. It 
allows for runtime additions to the e_flag by 
assembler directives. The standalone assembler can 
get to MCAssembler from getParser().getStreamer().getAssembler().

This patch is the generic infrastructure and will be
followed by patches for ARM and Mips for their target 
specific use.

Contributer: Jack Carter
 
llvm-svn: 173882
2013-01-30 02:09:52 +00:00
Michael J. Spencer
264c449666 [MC][COFF] Delay handling symbol aliases when writing
Fixes PR14447 and PR9034. Patch by Nico Rieck!

llvm-svn: 173839
2013-01-29 22:10:07 +00:00
Craig Topper
a8c721bc88 Merge SSE and AVX shuffle instructions in the comment printer.
llvm-svn: 173777
2013-01-29 07:54:31 +00:00
Craig Topper
8c275cea97 Fix 256-bit PALIGNR comment decoding to understand that it works on independent 256-bit lanes.
llvm-svn: 173674
2013-01-28 07:41:18 +00:00
Richard Osborne
373bdcfeb5 [XCore] Add missing l2rus instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173634
2013-01-27 22:28:30 +00:00
Richard Osborne
72f31f9da6 [XCore] Add missing l2r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173629
2013-01-27 21:26:02 +00:00
Richard Osborne
70183ce54a [XCore] Add missing 1r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173624
2013-01-27 20:46:21 +00:00
Richard Osborne
be996a5261 [XCore] Add missing 0r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173623
2013-01-27 20:42:57 +00:00
Benjamin Kramer
b7b4734d8b X86: Decode PALIGN operands so I don't have to do it in my head.
llvm-svn: 173572
2013-01-26 13:31:37 +00:00
Richard Osborne
32d4ba5aeb Add instruction encodings / disassembly support for l4r instructions.
llvm-svn: 173501
2013-01-25 21:55:32 +00:00
Eli Bendersky
027ead6802 Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,
use them in tests that run llvm-dwarfdump. This is in order to make tests as
specific as possible.

llvm-svn: 173498
2013-01-25 21:44:53 +00:00
Richard Osborne
4269c34e3d Add instruction encodings / disassembly support for l5r instructions.
llvm-svn: 173479
2013-01-25 20:20:07 +00:00
Jack Carter
26eec3af74 This patch implements parsing the .word
directive for the Mips assembler.

Contributer: Vladimir Medic
 
llvm-svn: 173407
2013-01-25 01:31:34 +00:00
Richard Osborne
8f90349114 Add instruction encodings / disassembly support for l6r instructions.
llvm-svn: 173288
2013-01-23 20:08:11 +00:00
Richard Osborne
6453bd631a Add instruction encodings / disassembly support for u10 / lu10 instructions.
llvm-svn: 173204
2013-01-22 22:55:04 +00:00
Kevin Enderby
042547700a Add a warning when there is a macro defintion that has named parameters but
the body does not use them and it appears the body has positional parameters.

This can cause unexpected results as in the added test case.  As the darwin
version of gas(1) which only supported positional parameters, happened to
ignore the named parameters.  Now that we want to support both styles of
macros we issue a warning in this specific case.

rdar://12861644

llvm-svn: 173199
2013-01-22 21:44:53 +00:00
Kevin Enderby
8bfddfebbb Have the integrated assembler give an error if $1 is used as an identifier in
an expression.  Currently this bug causes the line to be ignored in a
release build and an assert in a debug build.

rdar://13062484

llvm-svn: 173195
2013-01-22 21:09:20 +00:00
Eli Bendersky
ecccd87e5e Add forgotten test case for the x32 commit
llvm-svn: 173181
2013-01-22 18:52:39 +00:00
Benjamin Kramer
f2fc27452c X86: Make sure we account for the FMA4 register immediate value, otherwise rip-rel relocations will be off by one byte.
PR15040.

llvm-svn: 173176
2013-01-22 18:05:59 +00:00
Daniel Dunbar
26348eb62c [MC/Mach-O] Load commands are supposed to 8-byte aligned on 64-bit.
llvm-svn: 173120
2013-01-22 03:42:49 +00:00
Richard Osborne
02e7d3f377 Add instruction encodings / disassembly support for u6 / lu6 instructions.
llvm-svn: 173086
2013-01-21 20:44:17 +00:00
Richard Osborne
0b3c4f3112 Add instruction encoding / disassembly support for ru6 / lru6 instructions.
llvm-svn: 173085
2013-01-21 20:42:16 +00:00
Richard Osborne
c048ec5160 Add instruction encodings / disassembly support for l2rus instructions.
llvm-svn: 172987
2013-01-20 18:51:15 +00:00
Richard Osborne
5688672b0b Add instruction encodings / disassembly support for l3r instructions.
llvm-svn: 172986
2013-01-20 18:37:49 +00:00
Richard Osborne
400fb5329e Add instruction encodings / disassembler support for 2rus instructions.
llvm-svn: 172985
2013-01-20 17:22:43 +00:00
Richard Osborne
3a5e1fcceb Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

llvm-svn: 172984
2013-01-20 17:18:47 +00:00
Jack Carter
3f50a8d5c0 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Support for Mips register information sections.

Mips ELF object files have a section that is dedicated
to register use info. Some of this information such as
the assumed Global Pointer value is used by the linker
in relocation resolution.

The register info file is .reginfo in o32 and .MIPS.options
in 64 and n32 abi files.

This patch contains the changes needed to create the sections,
but leaves the actual register accounting for a future patch.


Contributer: Jack Carter
 
llvm-svn: 172847
2013-01-18 21:20:38 +00:00
Jack Carter
2737a54489 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

Removal of redundant code and formatting fixes.

Contributers: Jack Carter/Vladimir Medic
 
llvm-svn: 172842
2013-01-18 20:15:06 +00:00
Daniel Dunbar
bda778db3b [MC/Mach-O] Implement integrated assembler support for linker options.
- Also, fixup syntax errors in LangRef and missing newline in the MCAsmStreamer.

llvm-svn: 172837
2013-01-18 19:37:00 +00:00
Daniel Dunbar
1cb39fe210 [MC/Mach-O] Add support for linker options in Mach-O files.
llvm-svn: 172779
2013-01-18 01:26:07 +00:00
Daniel Dunbar
4f5f37798a [MC/Mach-O] Add AsmParser support for .linker_option directive.
llvm-svn: 172778
2013-01-18 01:25:48 +00:00
Jack Carter
fc7b77744d This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172685
2013-01-17 00:28:20 +00:00
Kevin Enderby
2e875dfb6d We want the dwarf AT_producer for assembly source files to match clang's
AT_producer.  Which includes clang's version information so we can tell
which version of the compiler was used.

This is the first of two steps to allow us to do that.  This is the llvm-mc
change to provide a method to set the AT_producer string.  The second step,
coming soon to a clang near you, will have the clang driver pass the value
of getClangFullVersion() via an flag when invoking the integrated assembler
on assembly source files.

rdar://12955296

llvm-svn: 172630
2013-01-16 17:46:23 +00:00
Jack Carter
6e4e11b877 reverting 172579
llvm-svn: 172594
2013-01-16 01:29:10 +00:00
Jack Carter
d951346d6e Akira,
Hope you are feeling better.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172579
2013-01-16 00:07:45 +00:00
Jack Carter
f7f756715f This patch fixes a Mips specific bug where
we need to generate a N64 compound relocation
R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE.

The bug was exposed by the SingleSourcetest case 
DuffsDevice.c.

Contributer: Jack Carter
llvm-svn: 172496
2013-01-15 01:08:02 +00:00
Chad Rosier
1f23c079a7 [ms-inline asm] Extend support for parsing Intel bracketed memory operands that
have an arbitrary ordering of the base register, index register and displacement.
rdar://12527141

llvm-svn: 172484
2013-01-14 22:31:35 +00:00
Jack Carter
d66ed8368e This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic
llvm-svn: 172284
2013-01-12 01:03:14 +00:00
Adhemerval Zanella
a2153405de PowerPC: EH adjustments
This patch adjust the r171506 to make all DWARF enconding pc-relative
for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT
(since the eh_frame will not generate PIC-relative relocation) and also
adds the emission of stubs created by the TTypeEncoding.

llvm-svn: 171979
2013-01-09 17:08:15 +00:00
Jack Carter
ac447a4205 This patch produces the correct addend value for
an R_MIPS_GPREL16 relocation.


Contributer: Jack Carter
llvm-svn: 171882
2013-01-08 19:01:28 +00:00
Jack Carter
f36167d718 This patch produces the correct pointer size
value in the 64 bit .eh_frame section.

It doesn't however allow exception handling to work
yet since it depends on the correct relocation model
being set in the ELF header flags.


Contributer: Jack Carter
llvm-svn: 171881
2013-01-08 18:53:20 +00:00
Eli Bendersky
2f7a1bfc7f Add some additional tests for the .bundle_lock align_to_end feature that didn't
make into the last commit.

Also, update the test-generation script to generate an exhaustive test for
align_to_end as well, and include the generated test.

llvm-svn: 171811
2013-01-07 23:12:59 +00:00