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Commit Graph

37556 Commits

Author SHA1 Message Date
Dylan McKay
1126d23533 [AVR] Fix signuature of AVRTargetMachine constructor
llvm-svn: 270292
2016-05-20 23:39:04 +00:00
Justin Bogner
20645f2085 SDAG: Implement Select instead of SelectImpl in PPCDAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
  the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

llvm-svn: 270283
2016-05-20 21:43:23 +00:00
Jacques Pienaar
4813cd5255 [lanai] Change reloc to use PIC_ by default and cleanup.
* Change reloc to PIC_;
* Cleanup (clang-format & modify test);

llvm-svn: 270282
2016-05-20 21:41:53 +00:00
David Majnemer
08b442df36 Address post-review for r270246
This gets rid of some unnecessary SmallStrings in
X86TargetMachine::getSubtargetImpl.

No functionality change is intended.

llvm-svn: 270270
2016-05-20 20:41:24 +00:00
Jun Bum Lim
3a259859b7 [AArch64] Disable narrow load merge by default
Summary:
As this optimization converts two loads into one load with two shift instructions,
it could potentially hurt performance if a loop is arithmetic operation intensive.

Reviewers: t.p.northover, mcrosier, jmolloy

Subscribers: evandro, jmolloy, aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D20172

llvm-svn: 270251
2016-05-20 18:45:49 +00:00
David Majnemer
7c0e6f025f [X86] Reduce memory allocations in X86TargetMachine::getSubtargetImpl
We performed a number of memory allocations each time getTTI was called,
remove them by using SmallString.
No functionality change intended.

llvm-svn: 270246
2016-05-20 18:16:06 +00:00
Sanjay Patel
d0547f1204 fix comments; NFC
llvm-svn: 270237
2016-05-20 17:07:19 +00:00
Sanjay Patel
2fd53c6d6b use range-loops; NFCI
llvm-svn: 270236
2016-05-20 17:00:10 +00:00
Sanjay Patel
56256e385a fix documentation comments; NFC
llvm-svn: 270234
2016-05-20 16:46:01 +00:00
Simon Pilgrim
95ba516d50 [X86][AVX] Generalized matching for target shuffle combines
This patch is a first step towards a more extendible method of matching combined target shuffle masks.

Initially this just pulls out the existing basic mask matches and adds support for some 256/512 bit equivalents. Future patterns will require a number of features to be added but I wanted to keep this patch simple.

I hope we can avoid duplication between shuffle lowering and combining and share more complex pattern match functions in future commits.

Differential Revision: http://reviews.llvm.org/D19198

llvm-svn: 270230
2016-05-20 16:19:30 +00:00
Rafael Espindola
3acc1df4cd Refactor X86 symbol access classification.
This refactors the logic in X86 to avoid code duplication. It also
splits it in two steps: it first decides if a symbol is local to the DSO
and then uses that information to decide how to access it.

The first part is implemented by shouldAssumeDSOLocal. It is not in any
way specific to X86. In a followup patch I intend to move it to
somewhere common and reused it in other backends.

llvm-svn: 270209
2016-05-20 12:20:10 +00:00
Rafael Espindola
8b4b8109e9 Simplify handling of hidden stubs on PowerPC.
We now handle them just like non hidden ones. This was already the case
on x86 (r207518) and arm (r207517).

llvm-svn: 270205
2016-05-20 12:00:52 +00:00
NAKAMURA Takumi
60e2685884 SparcISelLowering.cpp: Add missing StringSwitch.h
llvm-svn: 270200
2016-05-20 10:53:56 +00:00
Chris Dewhurst
1afaa64b44 [Sparc] Implement getRegisterByName.
Allows Sparc registers to be specifically referred to in inline assembly.

llvm-svn: 270198
2016-05-20 10:21:01 +00:00
Chris Dewhurst
08a87b67ef [Sparc] Enable more inline assembly constraints.
Note: This is specifically to allow GCC's test pr44707 to pass.

Trivial change, not put for differential revision. Test included.

llvm-svn: 270192
2016-05-20 09:03:01 +00:00
Craig Topper
1780b40874 [X86] Fix another AVX pattern to only be disable if VLX and BWI are supported.
llvm-svn: 270182
2016-05-20 05:10:27 +00:00
Jacques Pienaar
b966c4f1a6 [lanai] Use Optional<Reloc> in LanaiTargetMachine.
Follow r269988 and use Optional<Reloc>.

llvm-svn: 270176
2016-05-20 03:21:37 +00:00
Craig Topper
195c9b10ae [X86] Fix some AVX patterns to only be disabled if VLX and BWI are supported. Without this we get isel failures on the avx-intrinsics-x86.ll test in AVX512VL.
llvm-svn: 270174
2016-05-20 02:00:08 +00:00
Dylan McKay
e6c6905f3e Add AVRTargetStreamers
Reviewed by Matt Arsenault in http://reviews.llvm.org/D16311

llvm-svn: 270171
2016-05-20 01:17:38 +00:00
Rafael Espindola
62b7ba5ca2 Record a TargetMachine instead of a Reloc::Model.
Addresses r270095's code review.

llvm-svn: 270147
2016-05-19 22:07:57 +00:00
Matt Arsenault
e86632bcd4 AMDGPU: Remove pointless conversions
llvm-svn: 270139
2016-05-19 21:09:58 +00:00
Dan Gohman
0ad1ee502e [WebAssembly] Simplify code that never has to handle physical registers. NFC.
llvm-svn: 270137
2016-05-19 21:07:20 +00:00
David Blaikie
16fe2be1c3 Fix -Wunused-variable in non-Asserts build
llvm-svn: 270118
2016-05-19 20:44:22 +00:00
David Blaikie
5ded374dc4 Simplify conditional unreachable into an assertion
llvm-svn: 270111
2016-05-19 20:28:40 +00:00
Hans Wennborg
ff73dabfca X86: Don't reset the stack after calls that don't return (PR27117)
Since the calls don't return, the instruction afterwards will never run,
and is just taking up unnecessary space in the binary.

Differential Revision: http://reviews.llvm.org/D20406

llvm-svn: 270109
2016-05-19 20:15:33 +00:00
Rafael Espindola
4ed3f6e3d4 Remember the relocation model. NFC.
This avoids passing a TargetMachine in a few places.

llvm-svn: 270095
2016-05-19 18:49:29 +00:00
Rafael Espindola
084f91d955 Style fixes. NFC.
llvm-svn: 270093
2016-05-19 18:34:20 +00:00
Zhan Jun Liau
f045dd3779 [SystemZ] Test commit - remove idea from README
Remove a comment about not supporting LRVH/STRVH from the README
LRVH/STRVH are being generated as of r269688

llvm-svn: 270092
2016-05-19 18:30:17 +00:00
Matt Arsenault
31cc93c0d6 AMDGPU: Also look for s_cbranch_vccz
llvm-svn: 270091
2016-05-19 18:20:25 +00:00
Ron Lieberman
79c4da8069 Fix a covnersion from string to bool issue used in an assert
Problem Was exposed by -Wstring-conversion
    

llvm-svn: 270087
2016-05-19 18:05:56 +00:00
Chad Rosier
d705b5562f [AArch64 ] Generate a BFXIL from 'or (and X, Mask0Imm),(and Y, Mask1Imm)'.
Mask0Imm and ~Mask1Imm must be equivalent and one of the MaskImms is a shifted
mask (e.g., 0x000ffff0).  Both 'and's must have a single use.

This changes code like:

  and w8, w0, #0xffff000f
  and w9, w1, #0x0000fff0
  orr w0, w9, w8

into

  lsr w8, w1, #4
  bfi w0, w8, #4, #12

llvm-svn: 270063
2016-05-19 14:19:47 +00:00
Ranjeet Singh
7f495daec3 Test commit.
llvm-svn: 270056
2016-05-19 12:44:39 +00:00
Artem Tamazov
eea90f5cc7 [AMDGPU][llvm-mc] Fixes to support buffer atomics.
Fixes for MUBUF_Atomic instructions to make operand list valid:
 - For RTN insns, make a copy of $vdata_in operand as $vdata.
 - Do not add operand for GLC, it is hardcoded and comes as a token.
Workaround to avoid adding multiple default optional operands.
Tests added.

Differential Revision: http://reviews.llvm.org/D20257

llvm-svn: 270049
2016-05-19 12:22:39 +00:00
Zoran Jovanovic
07314a2bff ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocation
Differential Revision: http://reviews.llvm.org/D15526

llvm-svn: 270048
2016-05-19 12:20:40 +00:00
Daniel Sanders
7b472cd465 [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier.
Summary: Partially fixes PR27458

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20330

llvm-svn: 270037
2016-05-19 10:42:14 +00:00
Andrey Turetskiy
ccc62bdbb9 [X86] Enable RRL part of the LEA optimization pass for -O2.
Enable "Remove Redundant LEAs" part of the LEA optimization pass for -O2.
This gives 6.4% performance improve on Broadwell on nnet benchmark from Coremark-pro.
There is no significant effect on other benchmarks (Geekbench, Spec2000, Spec2006).

Differential Revision: http://reviews.llvm.org/D19659

llvm-svn: 270036
2016-05-19 10:18:29 +00:00
Zlatko Buljan
3d28e4b8d5 [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions
Differential Revision: http://reviews.llvm.org/D18352

llvm-svn: 270030
2016-05-19 07:31:28 +00:00
Craig Topper
1aff453749 [X86] Generalize and combine some similar type constraints and node types. No changes to the isel table size so the separation wasn't buying us anything.
llvm-svn: 270026
2016-05-19 06:13:58 +00:00
Craig Topper
c298b9dab5 [X86] Simplify some type constraints by removing parts that were already implied.
llvm-svn: 270025
2016-05-19 06:13:48 +00:00
Dan Gohman
bb2c8e5fad [WebAssembly] Update WebAssembly target for r269988.
llvm-svn: 270017
2016-05-19 03:00:05 +00:00
Craig Topper
4a761c4c76 [X86] Remove some type constraint classes and use already existing stricter classes.
llvm-svn: 270013
2016-05-19 02:05:58 +00:00
Craig Topper
f553944514 [AVX512] Strengthen type constraints for VFIXUPIMM patterns and combine the type constraints for vector and scalar.
llvm-svn: 270012
2016-05-19 02:05:55 +00:00
Chad Rosier
889772f9e3 [AArch64] Push comment into function. NFC.
llvm-svn: 270003
2016-05-18 23:51:17 +00:00
Matt Arsenault
6728e29c35 AMDGPU: Fix verifier error when spilling undef subreg
llvm-svn: 270002
2016-05-18 23:35:53 +00:00
Matt Arsenault
efc0ca4c19 AMDGPU: Fix promote alloca for pointer loads
If the load has a pointer type, we don't want to change
its type.

llvm-svn: 270000
2016-05-18 23:20:24 +00:00
Rafael Espindola
22e87bbb08 Delete Reloc::Default.
Having an enum member named Default is quite confusing: Is it distinct
from the others?

This patch removes that member and instead uses Optional<Reloc> in
places where we have a user input that still hasn't been maped to the
default value, which is now clear has no be one of the remaining 3
options.

llvm-svn: 269988
2016-05-18 22:04:49 +00:00
Jacques Pienaar
30194757f7 [lanai] Change the way flag setting instructions are checked.
isReturn() was returning different values with and without -g which led to
different code being generated. Change isFlagSettingInstruction to query
an instruction's effect on SR instead.

llvm-svn: 269986
2016-05-18 21:31:37 +00:00
Dan Gohman
2ff0f2e766 [WebAssembly] Disable the MachineScheduler.
llvm-svn: 269976
2016-05-18 20:19:02 +00:00
Jan Vesely
0f6b39e33f AMDGPU: Fix incorrect simm check
Use signed division otherwise all back jumps fail the check
Fixes regression introduced in r269951

Differential Revision: http://reviews.llvm.org/D20380

llvm-svn: 269972
2016-05-18 19:07:58 +00:00
Chad Rosier
4ef3f73429 [AArch64] Minor refactoring. NFC.
llvm-svn: 269963
2016-05-18 17:43:11 +00:00