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Commit Graph

2596 Commits

Author SHA1 Message Date
Kai Nacke
2ccf08db47 Fix alignment of unwind data.
For alignment purposes, the instruction array will always have an even
number of entries, with the final entry potentially unused (in which
case the array will be one longer than indicated by the count of unwind
codes field).

Reviewed by Charles Davis and Nico Rieck.

llvm-svn: 185760
2013-07-06 17:16:50 +00:00
Kai Nacke
3de8e2c2c3 Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEH
data structures.

The Win64 EH data structures must be of type IMAGE_REL_AMD64_ADDR32NB
instead of IMAGE_REL_AMD64_ADDR32. This is easiely achieved by adding
the VK_COFF_IMGREL32 modifier to the symbol reference.
Change also references to start and end of the SEH range of a function
as offsets to start of the function.

Reviewed by Charles Davis and Nico Rieck.

llvm-svn: 185759
2013-07-06 17:16:12 +00:00
Kai Nacke
7fc87e37dd Fix wrong code offset for unwind code SET_FPREG.
The code offset for unwind code SET_FPREG is wrong because it is set
to constant 0. The fix is to do the same as for the other unwind
codes: emit a label and later the absolute difference between the
label and the begin of the prologue.
Also enables the failing test case MC/COFF/seh.s

Reviewed by Charles Davis and Nico Rieck.

llvm-svn: 185758
2013-07-06 17:15:36 +00:00
Nico Rieck
fb7b696627 MC: Implement COFF .linkonce directive
llvm-svn: 185753
2013-07-06 12:13:10 +00:00
Ulrich Weigand
cbd8a1faa9 [PowerPC] Add some special @got@tprel fixup cases
When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.

However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.

The same applies for the @got@dtprel variants.

llvm-svn: 185700
2013-07-05 13:49:46 +00:00
Ulrich Weigand
23f9320617 [PowerPC] Make test case buildable with GNU as
The ppc64-fixups.s test currently fails to build with GNU as, since it
does not support plain symbols as arguments to li/lis.  Rewrite the test
for R_PPC64_ADDR16 and R_PPC64_REL16 to use lwz instead.

Allowing the test case to be built with both LLVM and GNU as makes it
easier to spot unwanted difference in the output.

llvm-svn: 185694
2013-07-05 12:33:03 +00:00
Ulrich Weigand
4fe8cda44b [PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
   add 3, 4, symbol@tls

The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant.  This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS.  This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.

As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.

llvm-svn: 185692
2013-07-05 12:22:36 +00:00
Nico Rieck
f688394960 MC: Add .section directive to COFF
Supports GAS flags "abdnrswxy". No support for alignment or subsections.

Fixes PR16366.

llvm-svn: 185669
2013-07-04 21:32:07 +00:00
Ulrich Weigand
ea65ed3cb6 [PowerPC] Implement writeNopData
This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.

This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.

llvm-svn: 185662
2013-07-04 18:28:46 +00:00
Rafael Espindola
eba3600903 Add 'not' in front of a command that is expected to fail.
llvm-svn: 185659
2013-07-04 17:21:01 +00:00
Joey Gouly
f5a82dca1f Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.

llvm-svn: 185642
2013-07-04 14:57:20 +00:00
Ulrich Weigand
cc940e19bb [PowerPC] Add all trap mnemonics
This adds support for all basic and extended variants
of the trap instructions to the asm parser.

llvm-svn: 185638
2013-07-04 14:40:12 +00:00
Ulrich Weigand
c602edd891 [PowerPC] Add asm parser support for CR expressions
This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".

llvm-svn: 185633
2013-07-04 14:24:00 +00:00
Joey Gouly
7a6dcc8db9 Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.
llvm-svn: 185620
2013-07-04 10:04:08 +00:00
Tilmann Scheller
07e970a22d ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.
Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.

The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.

This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.

Fixes <rdar://problem/14224440>.

llvm-svn: 185575
2013-07-03 20:38:01 +00:00
Ulrich Weigand
db2c0d673b [PowerPC] Support lmw/stmw in the asm parser
This adds support for the load/store multiple instructions,
currently used by the asm parser only.

llvm-svn: 185564
2013-07-03 18:29:47 +00:00
Ulrich Weigand
a5490843a1 [PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.

Current code however always emits mtcrf.  This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible.  It does create
inefficient code with the integrated assembler, however.

To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything.  Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.

As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.

llvm-svn: 185561
2013-07-03 17:59:07 +00:00
Rafael Espindola
006ee945bb Prefix failing commands with not to make clear they are expected to fail.
llvm-svn: 185554
2013-07-03 16:41:29 +00:00
Ulrich Weigand
33ba896ad1 [PowerPC] Support mtspr/mfspr in the asm parser
This adds support for the generic forms of mtspr/mfspr
for the asm parser.  The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.

llvm-svn: 185532
2013-07-03 12:32:41 +00:00
Mihai Popa
2403cfc9a6 This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits

llvm-svn: 185528
2013-07-03 09:21:44 +00:00
Ulrich Weigand
06e7a745ac [PowerPC] PR16512 - Support TLS call sequences in the asm parser
This patch now adds support for recognizing TLS call sequences in
the asm parser.  This needs a new pattern BL8_TLS, which is like
BL8_NOP_TLS except without nop.  That pattern is used for the
asm parser only.

llvm-svn: 185478
2013-07-02 21:31:59 +00:00
Richard Sandiford
bc31e83684 [SystemZ] Add the MVC instruction
This is the first use of D(L,B) addressing, which required a fair bit
of surgery.  For that reason, the patch just adds the instruction
definition and the associated assembler and disassembler support.
A later patch will actually make use of it for codegen.

llvm-svn: 185433
2013-07-02 14:56:45 +00:00
Logan Chien
83886dc182 Fix ARM EHABI compact model 1 and 2 without handlerdata.
According to ARM EHABI section 9.2, if the
__aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is
used, then the handler data must be emitted after the unwind
opcodes.  The handler data consists of several words, and
should be terminated by zero.

In case that the .handlerdata directive is not specified by
the programmer, we should emit zero to terminate the handler
data.

llvm-svn: 185422
2013-07-02 12:43:27 +00:00
Hal Finkel
4eba1c5685 Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
There are a couple of (small) related changes here:

1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.

2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).

3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.

4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.

With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.

llvm-svn: 185409
2013-07-02 03:39:34 +00:00
Ulrich Weigand
90cbe0a2da [PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
       .quad target@dtpmod
       .quad target@tprel
       .quad target@dtprel
Currently exploited by the asm parser only.

llvm-svn: 185394
2013-07-01 23:33:29 +00:00
Ulrich Weigand
534abefa5c [PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.

llvm-svn: 185387
2013-07-01 21:40:54 +00:00
Chad Rosier
54c8df1202 [ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values.  This should be the last fix due to fallout from r185094.

llvm-svn: 185379
2013-07-01 20:49:23 +00:00
Ulrich Weigand
4261958c61 [PowerPC] Also add "msync" alias
This adds an alias for "msync" (which is used on Book E
systems instead of "sync").

llvm-svn: 185375
2013-07-01 20:39:50 +00:00
Akira Hatanaka
3787fb8dc0 [mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.

llvm-svn: 185373
2013-07-01 20:31:44 +00:00
Ulrich Weigand
bd21c2da50 [PowerPC] Fix @got references to local symbols
A @got reference must always result in a relocation, so that
the linker has a chance to set up the GOT entry, even if the
symbol happens to be local.

Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces
a relocation to be emitted for GOT references.

llvm-svn: 185353
2013-07-01 18:19:56 +00:00
Ulrich Weigand
27e2e6a158 [PowerPC] Add "wait" instruction
This adds the "wait" instruction and its extended mnemonics.

llvm-svn: 185350
2013-07-01 17:21:23 +00:00
Ulrich Weigand
22cc4fd86f [PowerPC] Support "eieio" instruction
This adds support for the "eieio" instruction to
the asm parser.

llvm-svn: 185349
2013-07-01 17:06:26 +00:00
Ulrich Weigand
ec5b1279ef [PowerPC] Add some existing instructions to ppc64-encoding-bookII.s
The test case had a couple of FIXMEs where the instruction is in
fact already supported by the back-end.  In some other case, while
the generic form of the instruction is not yet supported, a
specialized form is.  This adds tests for those already supported
instructions / instruction forms.

llvm-svn: 185347
2013-07-01 16:52:55 +00:00
Ulrich Weigand
9dfc60786f [PowerPC] Add variants of "sync" instruction
This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".

llvm-svn: 185344
2013-07-01 16:37:52 +00:00
Serge Pavlov
8e65c835cb Added the test missed from r185080.
llvm-svn: 185316
2013-07-01 09:02:33 +00:00
Tilmann Scheller
9392d20bbe ARM: Fix pseudo-instructions for SRS (Store Return State).
The mapping between SRS pseudo-instructions and SRS native instructions was incorrect, the correct mapping is:

srsfa -> srsib
srsea -> srsia
srsfd -> srsdb
srsed -> srsda

This fixes <rdar://problem/14214734>.

llvm-svn: 185155
2013-06-28 15:09:46 +00:00
David Blaikie
a376b6ab57 Integrate Assembler: Support X86_64_DTPOFF64 relocations
llvm-svn: 185131
2013-06-28 04:24:32 +00:00
Chad Rosier
1ce13129c7 Improve the compression of the tablegen DiffLists by introducing a new sort
algorithm when assigning EnumValues to the synthesized registers.

The current algorithm, LessRecord, uses the StringRef compare_numeric
function.  This function compares strings, while handling embedded numbers.
For example, the R600 backend registers are sorted as follows:

  T1
  T1_W
  T1_X
  T1_XYZW
  T1_Y
  T1_Z
  T2
  T2_W
  T2_X
  T2_XYZW
  T2_Y
  T2_Z

In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2
have an EnumValue offset of 6 from one another.  However, in other parts
of the register bank, the scaling factors are different:

dEnum/dN = 5:
  KC0_128_W
  KC0_128_X
  KC0_128_XYZW
  KC0_128_Y
  KC0_128_Z
  KC0_129_W
  KC0_129_X
  KC0_129_XYZW
  KC0_129_Y
  KC0_129_Z

The diff lists do not work correctly because different kinds of registers have
different 'scaling factors'.  This new algorithm, LessRecordRegister, tries to
enforce a scaling factor of 1.  For example, the registers are now sorted as
follows:

  T1
  T2
  T3
  ...
  T0_W
  T1_W
  T2_W
  ...
  T0_X
  T1_X
  T2_X
  ...
  KC0_128_W
  KC0_129_W
  KC0_130_W
  ...

For the Mips and R600 I see a 19% and 6% reduction in size, respectively.  I
did see a few small regressions, but the differences were on the order of a
few bytes (e.g., AArch64 was 16 bytes).  I suspect there will be even
greater wins for targets with larger register files.

Patch reviewed by Jakob.
rdar://14006013

llvm-svn: 185094
2013-06-27 19:38:13 +00:00
Chad Rosier
2b164134e8 [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.

llvm-svn: 185026
2013-06-26 22:23:32 +00:00
Akira Hatanaka
677f305c97 [mips] Do not emit ".option pic0" if target is mips64.
llvm-svn: 185012
2013-06-26 19:08:49 +00:00
Tim Northover
2bf8ffa196 ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):

+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.

llvm-svn: 184965
2013-06-26 16:52:40 +00:00
Tim Northover
817190b1e4 ARM: allow predicated barriers in Thumb mode
The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.

llvm-svn: 184964
2013-06-26 16:52:32 +00:00
Ulrich Weigand
c2c8aeb508 [PowerPC] Accept 17-bit signed immediates for addis
The assembler currently strictly verifies that immediates for
s16imm operands are in range (-32768 ... 32767).  This matches
the behaviour of the GNU assembler, with one exception: gas
allows, as a special case, operands in an extended range
(-65536 .. 65535) for the addis instruction only (and its
extended mnemonic lis).

The main reason for this seems to be to allow using unsigned
16-bit operands for lis, e.g. like lis %r1, 0xfedc.

Since this has been supported by gas for a long time, and
assembler source code seen "in the wild" actually exploits
this feature, this patch adds equivalent support to LLVM
for compatibility reasons.

llvm-svn: 184946
2013-06-26 13:49:53 +00:00
Ulrich Weigand
66a94dc7aa [PowerPC] Support symbolic u16imm operands
Currently, all instructions taking s16imm operands support symbolic
operands.  However, for u16imm operands, we only support actual
immediate integers.  This causes the assembler to reject code like

  ori %r5, %r5, symbol@l

This patch changes the u16imm operand definition to likewise
accept symbolic operands.  In fact, s16imm and u16imm can
share the same encoding routine, now renamed to getImm16Encoding.

llvm-svn: 184944
2013-06-26 13:49:15 +00:00
Amaury de la Vieuville
8a7e3e2195 ARM: operands should be explicit when disassembled
llvm-svn: 184943
2013-06-26 13:39:07 +00:00
Ulrich Weigand
3e23cfcde6 [PowerPC] Support @got modifier
Add VK_... values and relocation types necessary to support
the @got family of modifiers.  Used by the asm parser only.

llvm-svn: 184860
2013-06-25 16:49:50 +00:00
Ulrich Weigand
e5affb6d66 [PowerPC] Add extended rotate/shift mnemonics
This adds all missing extended rotate/shift mnemonics to the asm parser.

llvm-svn: 184834
2013-06-25 13:17:41 +00:00
Ulrich Weigand
da66ee086f [PowerPC] Add rldcr/rldic instructions
This adds pattern for the rldcr and rldic instructions (the last instruction
from the rotate/shift family that were missing).  They are currently used
only by the asm parser.

llvm-svn: 184833
2013-06-25 13:17:10 +00:00
Ulrich Weigand
d51b3cd01b [PowerPC] Add extended subtract mnemonics
This adds support for the extended subtract mnemonics to the asm parser:
   subi
   subis
   subic
   subic.
   sub
   sub.
   subc
   subc.
 

llvm-svn: 184832
2013-06-25 13:16:48 +00:00
Ulrich Weigand
655ef3283d [PowerPC] Support some miscellaneous mnemonics in the asm parser
This adds support for the following extended mnemonics:
  xnop
  mr.
  not
  not.
  la

llvm-svn: 184767
2013-06-24 18:08:03 +00:00
Ulrich Weigand
ca3157e646 [PowerPC] Add some FIXMEs
A bunch of extendend mnemomics ought to support '.' forms.
Add FIXMEs to the test case for those.

llvm-svn: 184757
2013-06-24 17:00:22 +00:00
Ulrich Weigand
719e95004a [PowerPC] Add predicted forms of branches
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
  For these, I've added new PPC::Predicate codes corresponding
  to the BO values for predicted branch forms, and updated insn
  printing to print them correctly.  I've also added new aliases
  for the asm parser matching the new forms.
- bt/bf
  I've added new aliases matching to gBC etc.
- bd(n)z variants
  I've added new instruction patterns for the predicted forms.

In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)

llvm-svn: 184754
2013-06-24 16:52:04 +00:00
Ulrich Weigand
5349a508ea [PowerPC] Add t/f branch mnemonics to asm parser
This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the
asm parser, resolving to the generic conditional patterns.

llvm-svn: 184725
2013-06-24 12:49:20 +00:00
Ulrich Weigand
5f83058705 [PowerPC] Support generic conditional branches in asm parser
This adds instruction patterns to cover the generic forms of
the conditional branch instructions.  This allows the assembler
to support the generic mnemonics.

The compiler will still generate the various specific forms
of the instruction that were already supported.

llvm-svn: 184722
2013-06-24 11:55:21 +00:00
Ulrich Weigand
0dd44327b0 [PowerPC] Support absolute branches
There is currently only limited support for the "absolute" variants
of branch instructions.  This patch adds support for the absolute
variants of all branches that are currently otherwise supported.

This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.

While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.

No change in code generation intended.

llvm-svn: 184721
2013-06-24 11:03:33 +00:00
Ulrich Weigand
19b0f3dd0c [PowerPC] Support bd(n)zl and bd(n)zlrl
This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.

llvm-svn: 184720
2013-06-24 11:02:38 +00:00
Ulrich Weigand
5c11c4d795 [PowerPC] Support b(cond)l in the asm parser
This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.

llvm-svn: 184719
2013-06-24 11:02:19 +00:00
Ulrich Weigand
3a0dd840c3 [PowerPC] Support blrl and variants in the asm parser
This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.

llvm-svn: 184718
2013-06-24 11:01:55 +00:00
Amaury de la Vieuville
550e6ef18f ARM: check predicate bits for thumb instructions
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.

llvm-svn: 184707
2013-06-24 09:15:01 +00:00
Amaury de la Vieuville
37b2270352 ARM: rGPR is meant to be unpredictable, not undefined
llvm-svn: 184706
2013-06-24 09:14:54 +00:00
Amaury de la Vieuville
5a373a526e ARM: fix thumb1 nop decoding
In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.

llvm-svn: 184703
2013-06-24 09:11:53 +00:00
Amaury de la Vieuville
6eecd3f2cb ARM: fix IT decoding
mask == 0 -> UNPRED

llvm-svn: 184702
2013-06-24 09:11:45 +00:00
Amaury de la Vieuville
0d7ac788f2 ARM: enable decoding of pc-relative PLD/PLI
llvm-svn: 184701
2013-06-24 09:11:38 +00:00
Tim Northover
b9f0bb7e98 AArch64: fix overzealous NEXTing for Windows testing.
llvm-svn: 184667
2013-06-23 15:32:01 +00:00
Ulrich Weigand
3720d45002 [PowerPC] Support R_PPC_REL16 family of relocations
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:

  li 1, base-.

This patch adds support for those relocation types in the assembler.

llvm-svn: 184552
2013-06-21 14:44:37 +00:00
Ulrich Weigand
d5bb2945ff [PowerPC] Support various tls-related modifiers
The current code base only supports the minimum set of tls-related
relocations and @modifiers that are necessary to support compiler-
generated code.  This patch extends this to the full set defined
in the ABI (and supported by the GNU assembler) for the benefit
of the assembler parser.

llvm-svn: 184551
2013-06-21 14:44:15 +00:00
Ulrich Weigand
325653d5a4 [PowerPC] Support @higher et.al. modifiers
This adds support for the @higher, @highera, @highest, and @highesta
modifers, including some missing relocation types.

llvm-svn: 184550
2013-06-21 14:43:42 +00:00
Ulrich Weigand
283132010a [PowerPC] Support @toc@h modifier
This adds the relocation type and other necessary infrastructure
to use the @toc@h modifier in the assembler.

llvm-svn: 184549
2013-06-21 14:43:10 +00:00
Ulrich Weigand
02d460319a [PowerPC] Support @h modifier
This adds necessary infrastructure to support the @h modifier.
Note that all required relocation types were already present
(and unused).

This patch provides support for using @h in the assembler;
it would also be possible to now use this feature in code
generated by the compiler, but this is not done yet.

llvm-svn: 184548
2013-06-21 14:42:49 +00:00
Kevin Enderby
b71a2e2f2e Update the X86 disassembler to use xacquire and xrelease when appropriate.
This is a bit tricky as the xacquire and xrelease hints use the same bytes,
0xf2 and 0xf3, as the repne and rep prefixes.

Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease
and repne/xacquire. So to make this work a boolean was added the
InternalInstruction struct as part of the Prefix state which is set with the
added logic in readPrefixes() when decoding an instruction to determine
if these prefix bytes are to be disassembled as xacquire or xrelease.  Then
we let the matcher pick the normal prefix instructionID and we change the
Opcode after that when it is set into the MCInst being created.

rdar://11019859

llvm-svn: 184490
2013-06-20 22:32:18 +00:00
Joey Gouly
a600985f50 This reverts r155000.
The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.

VFP instructions on v8/AArch32 share the same encoding space as cdp2.

llvm-svn: 184445
2013-06-20 17:42:36 +00:00
Ulrich Weigand
8c70d558d3 [MC] Support @ variants with directional labels
The assembler parser common code supports recognizing symbol variants
using the @ modifer.  On PowerPC, it should also be possible to use
(some of) those modifiers with directional labels, like "1f@l".

This patch adds support for accepting symbol variants on directional
labels as well.

llvm-svn: 184437
2013-06-20 16:24:17 +00:00
Ulrich Weigand
99f0423d50 [PowerPC] Optimize @ha/@l constructs
This patch adds support for having the assembler optimize fixups
to constructs like "symbol@ha" or "symbol@l" if "symbol" can be
resolved at assembler time.

This optimization is already present in the PPCMCExpr.cpp code
for handling PPC_HA16/PPC_LO16 target expressions.  However,
those target expression were used only on Darwin targets.

This patch changes target expression code so that they are
usable also with the GNU assembler (using the @ha / @l syntax
instead of the ha16() / lo16() syntax), and changes the
MCInst lowering code to generate those target expressions
where appropriate.

It also changes the asm parser to generate HA16/LO16 target
expressions when parsing assembler source that uses the
@ha / @l modifiers.  The effect is that now the above-
mentioned optimization automatically becomes available
for those situations too.
 

llvm-svn: 184436
2013-06-20 16:23:52 +00:00
Ulrich Weigand
e143b13aca [PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).

This patch adds support for those extended compare mnemonics.


Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
 
 # CHECK: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
          cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128                 # encoding: [0x2c,0x23,0x00,0x80]
+         cmpdi 3, 128
 # CHECK: cmpd 2, 3, 4                    # encoding: [0x7d,0x23,0x20,0x00]
          cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4                    # encoding: [0x7c,0x23,0x20,0x00]
+         cmpd 3, 4
 # CHECK: cmpldi 2, 3, 128                # encoding: [0x29,0x23,0x00,0x80]
          cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128                # encoding: [0x28,0x23,0x00,0x80]
+         cmpldi 3, 128
 # CHECK: cmpld 2, 3, 4                   # encoding: [0x7d,0x23,0x20,0x40]
          cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4                   # encoding: [0x7c,0x23,0x20,0x40]
+         cmpld 3, 4
 
 # CHECK: cmpwi 2, 3, 128                 # encoding: [0x2d,0x03,0x00,0x80]
          cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128                 # encoding: [0x2c,0x03,0x00,0x80]
+         cmpwi 3, 128
 # CHECK: cmpw 2, 3, 4                    # encoding: [0x7d,0x03,0x20,0x00]
          cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4                    # encoding: [0x7c,0x03,0x20,0x00]
+         cmpw 3, 4
 # CHECK: cmplwi 2, 3, 128                # encoding: [0x29,0x03,0x00,0x80]
          cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128                # encoding: [0x28,0x03,0x00,0x80]
+         cmplwi 3, 128
 # CHECK: cmplw 2, 3, 4                   # encoding: [0x7d,0x03,0x20,0x40]
          cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4                   # encoding: [0x7c,0x03,0x20,0x40]
+         cmplw 3, 4
 
 # FIXME: Trap mnemonics
 
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
 defm : BranchExtendedMnemonic<"nu", 100>;
 defm : BranchExtendedMnemonic<"ns", 100>;
 
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+

llvm-svn: 184435
2013-06-20 16:15:12 +00:00
Vladimir Medic
af5979fc83 Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers.
llvm-svn: 184411
2013-06-20 11:21:49 +00:00
Ulrich Weigand
ef862011f0 [MC/DWARF] Generate multiple .debug_line entries for adjacent .loc directives
The compiler occasionally generates multiple .loc directives in a row
(at the same instruction address).  These need to be transformed into
multple actual .debug_line table entries, since they are used to signal
certain information to the debugger (e.g. if the opening brace of a
function body is on the same line as the declaration).

The MCAsmStreamer version of EmitDwarfLocDirective handles this
correctly by emitting a .loc directive every time it is called.
However, the MCObjectStream version simply defaults to recording
the information and emitting only a single table entry later,
e.g. when EmitInstruction is called.

This patch introduces a MCAsmStreamer::EmitDwarfLocDirective
version that emits a line table entry for a .loc directive
that may already be pending before recording the new directive.
(This is similar to how this is handled in GNU as.)

With this patch (and the code alignment factor patch) applied,
I'm now getting identical DWARF .debug sections for all test-suite
object files on PowerPC for the internal and the external assembler.

llvm-svn: 184357
2013-06-19 21:27:27 +00:00
Jim Grosbach
0f0c0ac8be ARM: Add optional datatype suffix to NEON mvn asm syntax.
rdar://14194152

llvm-svn: 184244
2013-06-18 21:49:21 +00:00
Kevin Enderby
cb41cc56c6 Change the arm assembler to support this from the v7c spec:
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."

In the pre-matcher handler in the asm parser the ".w" (wide) qualifier 
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.

Test cases for these were added.

rdar://14064574

llvm-svn: 184224
2013-06-18 20:19:24 +00:00
Jack Carter
016185840e Mips ELF: Mark object file as ABI compliant
When producing objects that are abi compliant we are 
marking neither the object file nor the assembly file
correctly and thus generate warnings. 

We need to set the EF_CPIC flag in the ELF header when
generating direct object.

Note that the warning is only generated when compiling without PIC.

When compiling with clang the warning will be suppressed by supplying:

 -Wa,-mno-shared -Wa,-call_nonpic

Also the following directive should also be added:

	.option	pic0

when compiling without PIC,  This eliminates the need for supplying:

  -mno-shared -call_nonpic

on the assembler command line.

Patch by Douglas Gilmore

llvm-svn: 184220
2013-06-18 19:47:15 +00:00
Stefanus Du Toit
aa267b3e82 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.

llvm-svn: 184207
2013-06-18 17:08:10 +00:00
Amaury de la Vieuville
0c0f005a15 ARM: fix literal load with positive offset encoding
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly

This patch also makes the assembler look at the .w/.n specifier for
loads.

llvm-svn: 184182
2013-06-18 08:13:05 +00:00
Amaury de la Vieuville
f28bf33894 ARM: add operands pre-writeback variants when needed
llvm-svn: 184181
2013-06-18 08:12:51 +00:00
Amaury de la Vieuville
8d8456b196 ARM: fix thumb literal loads decoding
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one

llvm-svn: 184180
2013-06-18 08:03:06 +00:00
Amaury de la Vieuville
e6ed8ad5df ARM: thumb stores cannot use PC as dest register
llvm-svn: 184179
2013-06-18 08:02:56 +00:00
Tim Northover
3231ab74d4 AArch64: print relocation addends if present on AArch64
llvm-objdump should provide some way of printing out the addends present in the
.rela sections for debugging purposes if nothing else.

llvm-svn: 184072
2013-06-17 03:03:06 +00:00
Amaury de la Vieuville
13c4894a31 ARM: fix thumb coprocessor instruction with pre-writeback disassembly
was        stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!

llvm-svn: 183975
2013-06-14 11:21:35 +00:00
Amaury de la Vieuville
6aadbcd8b4 ARM: fix B decoding
llvm-svn: 183914
2013-06-13 16:41:55 +00:00
Amaury de la Vieuville
6e5b103269 ARM: fix t2am_imm8_offset operand printing for imm=#-0
llvm-svn: 183913
2013-06-13 16:40:51 +00:00
Benjamin Kramer
f458149c7d X86: Make the cmov aliases work with intel syntax too.
llvm-svn: 183907
2013-06-13 15:45:24 +00:00
Ulrich Weigand
2666834190 [MC/DWARF] Support .debug_frame / .debug_line code alignment factors
I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.

In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4.  However, current MC code hard-codes a code
alignment factor of 1.

This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.

This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc.  Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available.  However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it.  If it turns out to be needed again at a later time, it
could be re-added with an updated interface.

llvm-svn: 183834
2013-06-12 14:46:54 +00:00
Ulrich Weigand
307b53fe55 [PowerPC] Use assembler source in MC tests
A couple of old test cases in test/MC/PowerPC were still using
LLVM IR.  Now that we have a working assembler, we can move
them to assembler tests instead:
  ppc64-initial-cfa.ll
  ppc64-relocs-01.ll
  ppc64-tls-relocs-01.ll

llvm-svn: 183829
2013-06-12 14:14:18 +00:00
NAKAMURA Takumi
bc128ca9be Rework r183728, suppress assert(0) for now. Its behavior depends on assertions on win32 hosts.
FIXME: Introduce yet another checker but assert(0).
llvm-svn: 183736
2013-06-11 10:01:42 +00:00
Mihai Popa
2b26ef36f1 It adds support for negative zero offsets for loads and stores.
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.

llvm-svn: 183734
2013-06-11 09:48:35 +00:00
Mihai Popa
30b6bcc387 This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
llvm-svn: 183733
2013-06-11 09:39:51 +00:00
Amaury de la Vieuville
334567de5c ARM: Enforce decoding rules for VLDn instructions
llvm-svn: 183731
2013-06-11 08:14:14 +00:00
Amaury de la Vieuville
896fff0d7e ARM: Fix STREX/LDREX reecoding
The decoded MCInst wasn't reencoded as the same instruction

llvm-svn: 183729
2013-06-11 08:03:20 +00:00
NAKAMURA Takumi
5bdf4d5248 Tweak a couple of tests on win32 hosts with +Asserts.
- Don't use assert(0), or tests may pass or fail according to assertions.
  - For now, The tests are marked as XFAIL for win32 hosts.

FIXME: Could we avoid XFAIL to specify triple in the RUN lines?
llvm-svn: 183728
2013-06-11 06:52:58 +00:00
Tim Northover
2ca847f56b ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.

rdar://14024354

llvm-svn: 183710
2013-06-10 23:20:58 +00:00
Ulrich Weigand
e6017e3db4 [PowerPC] Support extended sc mnemonic
A plain "sc" without argument is supposed to be treated like "sc 0"
by the assembler.  This patch adds a corresponding alias.

Problem reported by Joerg Sonnenberger.

llvm-svn: 183687
2013-06-10 17:19:43 +00:00
Ulrich Weigand
c6ff974cac [PowerPC] Support branch mnemonics with implied CR0
The extended branch mnemonics are supposed to use an implied CR0
if there is no explicit condition register specified.  This patch
adds extra variants of the mnemonics to this effect.

Problem reported by Joerg Sonnenberger.

llvm-svn: 183686
2013-06-10 17:19:15 +00:00