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Commit Graph

151306 Commits

Author SHA1 Message Date
Nemanja Ivanovic
b7abd5994a [PowerPC] Fix for PR33636
Remove casts to a constant when a node can be an undef.

Differential Revision: https://reviews.llvm.org/D34808

llvm-svn: 307120
2017-07-05 04:51:29 +00:00
Yuka Takahashi
878b347f79 [Bash-autocompletion] Show flags which has HelpText or GroupID
Summary: Otherwise internal flags will be also completed.

Differential Revision: https://reviews.llvm.org/D34930

llvm-svn: 307116
2017-07-05 02:36:32 +00:00
Nirav Dave
c3f1114c60 Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset
Relanding after rewriting undef.ll test to avoid host-dependant
endianness.

As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using
generic checks. Also, propagate missing local handling from there to
BaseIndexOffset checks.

Tests of note:

  * test/CodeGen/X86/build-vector* - Improved.
  * test/CodeGen/BPF/undef.ll - Improved store alignment allows an
    additional store merge

  * test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a
    case we already do not handle well. Here, the DAG is improved, but
    scheduling causes a code size degradation.

Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D34472

llvm-svn: 307114
2017-07-05 01:21:23 +00:00
Alexander Shaposhnikov
4bfc13da61 [profiledata] Avoid creating a temporary vector in getNumValueData
getValueSitesForKind returns ArrayRef which has a cast operator
to std::vector, as a result a temporary vector is created
if the type of the variable is const std::vector& 
that is suboptimal in this case.

Differential revision: https://reviews.llvm.org/D34970

Test plan: make check-all

llvm-svn: 307113
2017-07-05 01:20:52 +00:00
Anna Thomas
2f21b887d3 [SafepointIRVerifier] Add verifier pass for finding GC relocation bugs
Original Patch and summary by Philip Reames.

RewriteStatepointsForGC tries to rewrite a function in a manner where
the optimizer can't end up using a pointer value after it might have
been relocated by a safepoint. This pass checks the invariant that
RSForGC is supposed to establish and that (if we constructed semantics
correctly) later passes must preserve.

This has been a really useful diagnostic tool when initially developing
the rewriting scheme and has found numerous bugs.

Differential Revision: https://reviews.llvm.org/D15940

Reviewed by: swaroop.sridhar, mjacob

Subscribers: llvm-commits
llvm-svn: 307112
2017-07-05 01:16:29 +00:00
Dylan McKay
4df9fae587 Revert "[AVR] Add the branch selection pass from the GitHub repository"
This reverts commit 602ef067c1d58ecb425d061f35f2bc4c7e92f4f3.

llvm-svn: 307111
2017-07-05 00:50:56 +00:00
Dylan McKay
590d049bd1 [AVR] Add the branch selection pass from the GitHub repository
We should rewrite this using the generic branch relaxation pass, but for
the moment having this pass is better than hitting an assertion error.

llvm-svn: 307109
2017-07-05 00:41:19 +00:00
Gadi Haber
13cb50e549 NFC.
Made some updates to the half.ll test under CodeGen to make it friendly to the update_llc_test_checks .py tool as follows:
1.Removing the llc flag -asm-verbose=false
2.Grouping the multiple check-prefix directives
3.Apply update_llc_test_checks.py tool on the test

This change is needed to easily update scheduling changes in an upcoming patch.

Reviewers: zvi, RKSimon, craig.topper 

Differential Revision: https://reviews.llvm.org/D34934

llvm-svn: 307108
2017-07-04 21:51:05 +00:00
Craig Topper
53882d70f0 Recommit r307064, "[InstCombine] Add test cases demonstrating creation of extra bswap instrinsic calls when when optimizing bswap and bitwise ops when the bswaps have additional uses. NFC"
The test check lines have now been fixed.

llvm-svn: 307106
2017-07-04 20:15:24 +00:00
Andrew Zhogin
c78e525e6b [ARM][test] Added test/CodeGen/ARM/ror.ll test. NFC precommit for D12833.
llvm-svn: 307103
2017-07-04 19:50:22 +00:00
Simon Pilgrim
96f5744476 [X86][SSE4A] Add support for combining from non-v16i8 EXTRQI/INSERTQI shuffles
With the improved shuffle decoding we can now combine EXTRQI/INSERTQI shuffles from non-v16i8 vector types

llvm-svn: 307099
2017-07-04 18:11:02 +00:00
Simon Pilgrim
42a63cca1a Fix signed/unsigned comparison warnings
llvm-svn: 307098
2017-07-04 17:42:01 +00:00
Alexander Timofeev
71cf453d98 [AMDGPU] Switch scalarize global loads ON by default
Differential revision: https://reviews.llvm.org/D34407

llvm-svn: 307097
2017-07-04 17:32:00 +00:00
Anna Thomas
289d0ebad4 [LoopDeletion] NFC: Add loop being analyzed debug statement
llvm-svn: 307096
2017-07-04 17:00:03 +00:00
Simon Pilgrim
e2ac627557 [X86][SSE4A] Generalized EXTRQI/INSERTQI shuffle decodes
The existing decodes only worked for v16i8 vectors, this adds support for any 128-bit vector

llvm-svn: 307095
2017-07-04 16:53:12 +00:00
Hiroshi Inoue
8c9589ce3a fix trivial typos in comments; NFC
llvm-svn: 307094
2017-07-04 16:35:26 +00:00
Daniel Sanders
177fc6453d [globalisel][tablegen] Fix the modules build after r307079
Exclude InstructionSelectorImpl.h since DEBUG_TYPE may vary between includes.

llvm-svn: 307093
2017-07-04 16:29:38 +00:00
Andrew Zhogin
0d027b7284 [DAGCombiner] Intermediate variables in visitRotate promoted to the function's begin. NFC precommit for D12833.
llvm-svn: 307091
2017-07-04 15:57:39 +00:00
Daniel Sanders
30c3678129 [globalisel][tablegen] Fix release builds after r307079
Using NumPatternEmitted as a unique id for the tables is not valid on release
builds since the counters don't count in that case.

Also fix an unused variable warning.

llvm-svn: 307088
2017-07-04 15:31:50 +00:00
Anna Thomas
e7c8763550 [FastISel] Move gc intrinsic test to X86 directory
Move from generic to X86 directory since gc intrinsics only supposed in
X86 64 bit.
Add target triple as well.
Fixes build failure in i686-linux-RA  caused by rL307084.

llvm-svn: 307086
2017-07-04 15:24:08 +00:00
Alexander Kornienko
5c84ab0bec Fix dangling StringRefs found by clang-tidy misc-dangling-handle check.
llvm-svn: 307085
2017-07-04 15:13:02 +00:00
Anna Thomas
9d7382c30f [FastISel][SelectionDAG]Teach fastISel about GC intrinsics
Summary:
We are crashing in LLC at O0 when gc intrinsics are present in the block.
The reason being FastISel performs basic block ISel by modifying GC.relocates
to be the first instruction in the block. This can cause us to visit the GC
relocate before it's corresponding GC.statepoint is visited, which is incorrect.
When we lower the statepoint, we record the base and derived pointers, along
with the gc.relocates. After this we can visit the gc.relocate.

This patch avoids fastISel from incorrectly creating the block with gc.relocate
as the first instruction.

Reviewers: qcolombet, skatkov, qikon, reames

Reviewed by: skatkov

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34421

llvm-svn: 307084
2017-07-04 15:09:09 +00:00
Marek Olsak
518ccca66b [AMDGPU] Fix latency of MIMG instructions
Patch by cwabbott (Connor Abbott).

llvm-svn: 307081
2017-07-04 14:43:38 +00:00
Ilya Biryukov
5ce674cda2 NFC. Removed mention of missing script from build_docker_image.sh.
llvm-svn: 307080
2017-07-04 14:41:21 +00:00
Daniel Sanders
f4173f55ab [globalisel][tablegen] Partially fix compile-time regressions by converting matcher to state-machine(s)
Summary:
Replace the matcher if-statements for each rule with a state-machine. This
significantly reduces compile time, memory allocations, and cumulative memory
allocation when compiling AArch64InstructionSelector.cpp.o after r303259 is
recommitted.

The following patches will expand on this further to fully fix the regressions.

Reviewers: rovka, ab, t.p.northover, qcolombet, aditya_nandakumar

Reviewed By: ab

Subscribers: vitalybuka, aemerson, javed.absar, igorb, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D33758

llvm-svn: 307079
2017-07-04 14:35:06 +00:00
Anna Thomas
690b0b954d [LoopDeletion] NFC: Add debug statements to the optimization
We have a DEBUG option for loop deletion, but no related debug messages.
Added some debug messages to state why loop deletion failed.

llvm-svn: 307078
2017-07-04 14:05:19 +00:00
Hiroshi Inoue
b8f3b6269d fix trivial typos in comments; NFC
llvm-svn: 307075
2017-07-04 13:09:29 +00:00
Simon Pilgrim
667b0a48a0 [X86] Add combine tests for vector rotates
Reference tests for D12833

llvm-svn: 307073
2017-07-04 12:33:53 +00:00
NAKAMURA Takumi
68b69d4c27 Revert r307064, "[InstCombine] Add test cases demonstrating creation of extra bswap instrinsic calls when when optimizing bswap and bitwise ops when the bswaps have additional uses. NFC"
Seems confused between %tmpN and unnamed %N to give same name.

llvm-svn: 307070
2017-07-04 12:13:27 +00:00
NAKAMURA Takumi
6b82d26fee llvm/ExecutionEngine/Orc/ObjectTransformLayer.h: Add <memory> to appease libstdc++'s std::shared_ptr.
llvm-svn: 307069
2017-07-04 12:12:37 +00:00
Gadi Haber
7d3b16bb46 NFC commit.
Converting the Codegen test "extractelement-legalization-store-ordering.ll" to be "update_llc_test_checks" friendly.

The changes to the test are needed for an upcoming scheduling patch.

Reviewers: zvi, RKSimon

Differential Revision: https://reviews.llvm.org/D34935

llvm-svn: 307066
2017-07-04 07:18:03 +00:00
Craig Topper
fd4b958ec9 [InstCombine] Add TODOs for a couple things that should maybe be in InstSimplify instead. NFC
llvm-svn: 307065
2017-07-04 06:50:48 +00:00
Craig Topper
c1b931dafe [InstCombine] Add test cases demonstrating creation of extra bswap instrinsic calls when when optimizing bswap and bitwise ops when the bswaps have additional uses. NFC
I assume bswap intrinsics are somewhat costly so we should be making sure we are getting rid of them not creating more.

llvm-svn: 307064
2017-07-04 06:50:44 +00:00
Alexander Shaposhnikov
c76d1c1edb [tablegen] Avoid creating a temporary vector in getInstructionCase
Record::getValues returns ArrayRef which has a cast operator
to std::vector, as a result a temporary vector is created
if the type of the variable is const std::vector& 
that is suboptimal in this case.

Differential revision: https://reviews.llvm.org/D34969

Test plan: make check-all

llvm-svn: 307063
2017-07-04 06:16:53 +00:00
Craig Topper
59ed8390ed [X86] Add comment string for broadcast loads from the constant pool.
Summary:
When broadcasting from the constant pool its useful to print out the final vector similar to what we do for normal moves from the constant pool.

I changed only a couple tests that were broadcast focused. One of them had been previously hand tweaked after running the script so that it could check the constant pool declaration. But I think this patch makes that unnecessary now since we can check the comment instead.

Reviewers: spatel, RKSimon, zvi

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34923

llvm-svn: 307062
2017-07-04 05:46:11 +00:00
Alexander Shaposhnikov
1a21ff1278 [llvm] Revert "[tablegen] Avoid creating a temporary vector in getInstructionCase"
Revert rL307059 because of the incorrect commit message & patch, 
will recommit later.

llvm-svn: 307061
2017-07-04 05:37:37 +00:00
Craig Topper
da8c8afca2 [X86] Add RDRAND feature to GLM CPU
Summary: I believe this should be supported on GLM since RDSEED is.

Reviewers: m_zuckerman, zvi, RKSimon

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34828

llvm-svn: 307060
2017-07-04 05:33:19 +00:00
Alexander Shaposhnikov
8ae1bcfa19 [tablegen] Avoid creating a temporary vector in getInstructionCase
Record::getValues returns ArrayRef which has a cast operator
to std::vector, as a result a temporary vector is created
if the type of the variable is const std::vector& 
that was suboptimal in this case.

Differential revision: https://reviews.llvm.org/D34969

Test plan: make check-all

llvm-svn: 307059
2017-07-04 05:11:30 +00:00
Lang Hames
5ffd7d4185 [Orc] Remove the memory manager argument to addModule, and de-templatize the
symbol resolver argument.

De-templatizing the symbol resolver is part of the ongoing simplification of
ORC layer API.

Removing the memory management argument (and delegating construction of memory
managers for RTDyldObjectLinkingLayer to a functor passed in to the constructor)
allows us to build JITs whose base object layers need not be compatible with
RTDyldObjectLinkingLayer's memory mangement scheme. For example, a 'remote
object layer' that sends fully relocatable objects directly to the remote does
not need a memory management scheme at all (that will be handled by the remote).

llvm-svn: 307058
2017-07-04 04:42:30 +00:00
Dylan McKay
71adee46e4 [AVR] Fix bug which caused assertion errors for some FRMIDX instructions
Previously, if a basic block ended with a FRMIDX instruction, we would
end up doing something like this.

*std::next(MBB.end())

Which would hit an error:

"Assertion `!NodePtr->isKnownSentinel()' failed."

llvm-svn: 307057
2017-07-04 04:40:06 +00:00
Dylan McKay
e74f1e970e [AVR] Add a missing clobber declaration to LPMW
llvm-svn: 307056
2017-07-04 02:52:43 +00:00
Nirav Dave
d98172f6a7 [DAG] Fixed predicate for determining when two frame indices
addresses are comparable. NFCI.

llvm-svn: 307055
2017-07-04 02:20:17 +00:00
NAKAMURA Takumi
e6c7524092 Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"
It broke a testcase.

  Failing Tests (1):
      LLVM :: CodeGen/AMDGPU/alignbit-pat.ll

llvm-svn: 307054
2017-07-04 02:14:18 +00:00
Anton Yartsev
0649b527ea [legalize-types] Clean up softening machinery.
The patch makes SoftenFloatResult/Operand logic just the same as all other legalization routines have: SoftenFloatResult() now fills the SoftenFloats map and SoftenFloatOperand() perform all needed replacements. This prevents softening mashinery from leaving stale entries in SoftenFloats map (that resulted in errors during the legalize type checking) and clarifies softening. The patch replaces https://reviews.llvm.org/D29265.

Differential Revision: https://reviews.llvm.org/D31946

llvm-svn: 307053
2017-07-04 01:08:55 +00:00
Simon Pilgrim
b4da2dc3af [X86][SSE4A] Add support for combining from EXTRQI/INSERTQI shuffles
llvm-svn: 307048
2017-07-03 20:58:16 +00:00
Zvi Rackover
3f342ef7af MathExtras UnitTest: Assert that isPowerOf2(0) is false. NFC.
Summary:
This is a follow-up on D34077. Elena observed that the
correctness of the code relies on isPowerOf2(0) returning false.
Adding a test to cover this corner-case.

Reviewers: delena, davide, craig.topper

Reviewed By: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34939

llvm-svn: 307046
2017-07-03 18:42:47 +00:00
Simon Pilgrim
a1dd87c298 [X86][SSE4A] Add SSE4A shuffle tests on pre-SSSE3 hardware
llvm-svn: 307042
2017-07-03 16:53:11 +00:00
Simon Pilgrim
66be995978 [X86][SSE4A] Test SSE4A shuffle combining on SSE42 capable target as well
llvm-svn: 307038
2017-07-03 15:55:54 +00:00
Zvi Rackover
e1f310fac6 DAGCombine: Combine BUILD_VECTOR to TRUNCATE
Summary:
Add a combine for creating a truncate to replace a build_vector composed of extracts with
indices that form a stride-2^N series.

Example:
v8i32 V = ...

v4i32 build_vector((extract_elt V, 0), (extract_elt V, 2), (extract_elt V, 4), (extract_elt V, 6))
-->
v4i32 truncate (bitcast V to v4i64)

Related discussion in llvm-dev about canonicalizing shuffles to
truncates in LLVM IR:
http://lists.llvm.org/pipermail/llvm-dev/2017-January/108936.html.

Reviewers: spatel, RKSimon, efriedma, igorb, craig.topper, wolfgangp, delena

Reviewed By: delena

Subscribers: guyblank, delena, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D34077

llvm-svn: 307036
2017-07-03 15:47:40 +00:00
Florian Hahn
80a9b3cbaf [LoopInterchange] Add more debug messages to currentLimitations().
Summary: This makes it easier to find out which limitation prevented this pass from doing its work.

Reviewers: karthikthecool, mzolotukhin, efriedma, mcrosier

Reviewed By: mcrosier

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D34940

llvm-svn: 307035
2017-07-03 15:32:00 +00:00