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Author SHA1 Message Date
Jim Grosbach
3e9384b103 ARM NEON two-operand aliases for VSHL(register). 
llvm-svn: 146123
 2011-12-08 01:12:35 +00:00
Jakob Stoklund Olesen
533f7a0f7a Simplify offset verification. 
llvm-svn: 146121
 2011-12-08 01:10:05 +00:00
Jim Grosbach
1ec6357689 Fix copy/past-o. 
llvm-svn: 146120
 2011-12-08 01:02:26 +00:00
Jim Grosbach
7e59d1c4db ARM NEON two-operand aliases for VMUL. 
llvm-svn: 146119
 2011-12-08 00:59:47 +00:00
Jakob Stoklund Olesen
ff1463af3b Don't include alignment padding in BBInfo.Size. 
Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

llvm-svn: 146118
 2011-12-08 00:55:02 +00:00
Jim Grosbach
597cb99d62 ARM VFP support 'fmrs/fmsr' aliases for 'vldr' 
llvm-svn: 146116
 2011-12-08 00:52:55 +00:00
Jim Grosbach
fa73a483a9 ARM VFP support 'flds/fldd' aliases for 'vldr' 
llvm-svn: 146115
 2011-12-08 00:49:29 +00:00
Jim Grosbach
3b4d5c0510 ARM optional destination operand variants for VEXT instructions. 
llvm-svn: 146114
 2011-12-08 00:43:47 +00:00
Jim Grosbach
0c64182f7c Tidy up. 
llvm-svn: 146113
 2011-12-08 00:41:54 +00:00
Chad Rosier
77c21bef26 Fix 80-column. 
Simplify code.

llvm-svn: 146112
 2011-12-08 00:38:45 +00:00
Jim Grosbach
c1cf417595 ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
llvm-svn: 146111
 2011-12-08 00:31:07 +00:00
Nick Lewycky
fc10724777 Add Tsan annotations to the pass system. 
Perhaps once(&func) should be hoisted into lib/Support.

llvm-svn: 146110
 2011-12-08 00:15:41 +00:00
Chad Rosier
84833a551a Fix comments. 
llvm-svn: 146109
 2011-12-08 00:11:31 +00:00
Peter Collingbourne
7f575840c2 EngineBuilder: support for custom TargetOptions. Fixes the 
ExceptionDemo example.

llvm-svn: 146108
 2011-12-07 23:58:57 +00:00
Chad Rosier
3a984f96d7 Fix comments. 
llvm-svn: 146107
 2011-12-07 23:57:55 +00:00
Jim Grosbach
6146f79b7d ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

llvm-svn: 146106
 2011-12-07 23:40:58 +00:00
Akira Hatanaka
5c18dd9da0 Modify class ReadHardware and add definition of 64-bit version of instruction 
RDHWR. 

llvm-svn: 146101
 2011-12-07 23:31:26 +00:00
Akira Hatanaka
9aac8897da Add newline. 
llvm-svn: 146100
 2011-12-07 23:26:03 +00:00
Akira Hatanaka
5b94220d32 Add 64-bit HWR29 register. 
llvm-svn: 146099
 2011-12-07 23:23:52 +00:00
Akira Hatanaka
dcdd599065 32 to 64-bit anyext pattern. 
llvm-svn: 146097
 2011-12-07 23:21:19 +00:00
Akira Hatanaka
7db0038ac0 32 to 64-bit zext pattern. 
llvm-svn: 146096
 2011-12-07 23:14:41 +00:00
Jim Grosbach
dd3788b044 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
llvm-svn: 146095
 2011-12-07 23:08:12 +00:00
Jim Grosbach
da0a3e310a ARM two-operand aliases for VADDW instructions. 
llvm-svn: 146093
 2011-12-07 23:01:10 +00:00
Jim Grosbach
ecf9c2bb21 ARM two-operand aliases for VADD instructions. 
llvm-svn: 146091
 2011-12-07 22:52:54 +00:00
Chad Rosier
8fa56304bd Flesh out a bit more of the bitcode use-list ordering preservation code. 
Nothing too interesting at this point, but comments are welcome.
Part of rdar://9860654 and PR5680.

llvm-svn: 146090
 2011-12-07 22:49:05 +00:00
Bruno Cardoso Lopes
96a462ec03 Variable cleanup. Based on past patch submittals variable names have 
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.

llvm-svn: 146088
 2011-12-07 22:35:30 +00:00
Eli Friedman
e68dd964f7 Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling. 
llvm-svn: 146087
 2011-12-07 22:24:28 +00:00
Akira Hatanaka
b8e63b4c07 64-bit WrapperPICPat patterns. 
llvm-svn: 146086
 2011-12-07 22:11:43 +00:00
Daniel Dunbar
a04ceeeedc configure: Don't warn about compiler-rt checked out into projects/. 
llvm-svn: 146084
 2011-12-07 22:07:03 +00:00
Eli Friedman
333928a702 Fix an assertion in the scheduler. PR11386. No testcase included because it's rather delicate. 
llvm-svn: 146083
 2011-12-07 22:06:02 +00:00
Akira Hatanaka
61b72249eb Define base class for WrapperPICPat. 
llvm-svn: 146081
 2011-12-07 21:54:54 +00:00
Akira Hatanaka
2b45547782 Modify LowerFCOPYSIGN to handle Mips64. 
llvm-svn: 146080
 2011-12-07 21:48:50 +00:00
Chad Rosier
e3225d38e4 Update bcanalyzer to handle new USELIST_BLOCK/USELIST_CODE_ENTRY. 
llvm-svn: 146079
 2011-12-07 21:45:13 +00:00
Chad Rosier
9e2206651f Begin adding experimental support for preserving use-list ordering of bitcode 
files.  First, add a new block USELIST_BLOCK to the bitcode format.  This is 
where USELIST_CODE_ENTRYs will be stored.  The format of the USELIST_CODE_ENTRYs
have not yet been defined.  Add support in the BitcodeReader for parsing the
USELIST_BLOCK.
Part of rdar://9860654 and PR5680.

llvm-svn: 146078
 2011-12-07 21:44:12 +00:00
Nick Lewycky
9139ac9fdb These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me 
that he isn't using these any more, so just delete them.

llvm-svn: 146076
 2011-12-07 21:35:59 +00:00
Duncan Sands
cc43a2e4fd Have cmake build llvm-cov. Patch by arrowdodger. 
llvm-svn: 146071
 2011-12-07 20:54:41 +00:00
Chad Rosier
cbfc33c233 ValueEnumerator - debug dump(). 
llvm-svn: 146070
 2011-12-07 20:44:46 +00:00
Akira Hatanaka
b170dc0eff Fix comment. 
llvm-svn: 146063
 2011-12-07 20:15:01 +00:00
Akira Hatanaka
e5c8837ed0 Fix comment. 
llvm-svn: 146062
 2011-12-07 20:13:53 +00:00
Akira Hatanaka
19d6cd4d0e Fix 64-bit immediate patterns. 
llvm-svn: 146059
 2011-12-07 20:10:24 +00:00
Jim Grosbach
268b95034c Nuke inadvertant debugging commit. 
llvm-svn: 146057
 2011-12-07 19:56:16 +00:00
Jim Grosbach
2f57374e32 Darwin assembler improved relocs when w/o subsections_via_symbols. 
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.

llvm-svn: 146054
 2011-12-07 19:46:59 +00:00
Jakub Staszak
a8a18f2cf5 Remove unneeded semicolon. 
Skip two looking up at BlockChain.

llvm-svn: 146053
 2011-12-07 19:46:10 +00:00
Jim Grosbach
1ccae84fa7 Thumb2 alias for long-form pop and friends. 
rdar://10542474

llvm-svn: 146046
 2011-12-07 18:32:28 +00:00
Bill Wendling
31110c8c27 Also pass in correct initializer here. 
llvm-svn: 146044
 2011-12-07 18:18:11 +00:00
Jim Grosbach
81cb9952c9 ARM support the .arm and .thumb directives for assembly mode switching. 
llvm-svn: 146042
 2011-12-07 18:04:19 +00:00
Bill Wendling
e335d0861c Correct initializer in example. 
llvm-svn: 146041
 2011-12-07 18:02:44 +00:00
Jim Grosbach
3352ab97ca ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
llvm-svn: 146039
 2011-12-07 17:51:15 +00:00
Jim Grosbach
61d2b8b2f9 Tidy up. Move MachO tests to MachO directory. 
llvm-svn: 146038
 2011-12-07 17:50:28 +00:00
Duncan Sands
8b1c4875c3 Remove unused include. 
llvm-svn: 146037
 2011-12-07 17:18:31 +00:00