RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 22:42:46 +02:00
Code Issues Projects Releases Wiki Activity
22,964 Commits 4 Branches 5 Tags 704 MiB
183b913508
Commit Graph

840 Commits

Author SHA1 Message Date
Evan Cheng
183b913508 Added isOperand(N): true if this is an operand of N 
llvm-svn: 26501
 2006-03-03 06:24:54 +00:00
Evan Cheng
b91460b269 A bit more tweaking 
llvm-svn: 26500
 2006-03-03 06:23:43 +00:00
Jeff Cohen
ee1a26dc07 Fix VC++ compilation errors. 
llvm-svn: 26498
 2006-03-03 03:25:07 +00:00
Chris Lattner
999aa36a04 remove the read/write port/io intrinsics. 
llvm-svn: 26479
 2006-03-03 00:19:58 +00:00
Chris Lattner
ab22220755 Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving 
PR709, and paving the way for future progress.

llvm-svn: 26476
 2006-03-03 00:00:25 +00:00
Evan Cheng
71fa36ef12 - Fixed some priority calculation bugs that were causing bug 478. Among them: 
a predecessor appearing more than once in the operand list was counted as
  multiple predecessor; priority1 should be updated during scheduling;
  CycleBound was updated after the node is inserted into priority queue; one
  of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
  operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
  predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
        .text
        .align  4
        .globl  _f
_f:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        movl %eax, %edx
        imull %ecx, %edx
        imull %eax, %eax
        imull %ecx, %ecx
        addl %eax, %ecx
        leal (%ecx,%edx,2), %eax
        ret

  It is also a slight performance win (1% - 3%) for most tests.

llvm-svn: 26470
 2006-03-02 21:38:29 +00:00
Chris Lattner
d45d3b68b0 Fix CodeGen/Generic/2006-03-01-dagcombineinfloop.ll, an infinite loop 
in the dag combiner on 176.gcc on x86.

llvm-svn: 26459
 2006-03-01 21:47:21 +00:00
Chris Lattner
5544c94289 Fix a typo evan noticed 
llvm-svn: 26454
 2006-03-01 19:55:35 +00:00
Chris Lattner
6434a21c21 Add support for target-specific dag combines 
llvm-svn: 26443
 2006-03-01 04:53:38 +00:00
Chris Lattner
f571b8c5dd Add a new AddToWorkList method, start using it 
llvm-svn: 26441
 2006-03-01 04:03:14 +00:00
Chris Lattner
7ba1c5e025 Pull shifts by a constant through multiplies (a form of reassociation), 
implementing Regression/CodeGen/X86/mul-shift-reassoc.ll

llvm-svn: 26440
 2006-03-01 03:44:24 +00:00
Evan Cheng
d8b92e04a2 Vector ops lowering. 
llvm-svn: 26436
 2006-03-01 01:09:54 +00:00
Evan Cheng
2cbf9d93d3 - Added VConstant as an abstract version of ConstantVec. 
- All abstrct vector nodes must have # of elements and element type as their
first two operands.

llvm-svn: 26432
 2006-03-01 00:51:13 +00:00
Chris Lattner
3aa1cd759e Compile: 
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }

to:

_foo4:
        lbz r3,1(r3)
        blr
_foo5:
        lbz r3,1(r3)
        blr

not:

_foo4:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr
_foo5:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

llvm-svn: 26419
 2006-02-28 06:49:37 +00:00
Chris Lattner
24a22066c4 Fold "and (LOAD P), 255" -> zextload. This allows us to compile: 
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
        lbz r3, 3(r3)
        blr

instead of:

_foo3:
        lwz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

and:

unsigned short foo2(float a) { return a; }

as:
_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lhz r3, -2(r1)
        blr

instead of:

_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

llvm-svn: 26417
 2006-02-28 06:35:35 +00:00
Chris Lattner
152201257d fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 
llvm-svn: 26416
 2006-02-28 06:23:04 +00:00
Chris Lattner
a451b5ffd4 Add support for output memory constraints. 
llvm-svn: 26410
 2006-02-27 23:45:39 +00:00
Chris Lattner
baea29f33d remove some completed notes 
llvm-svn: 26390
 2006-02-27 00:39:31 +00:00
Evan Cheng
5abf5b2ce4 Print ConstantPoolSDNode offset field. 
llvm-svn: 26381
 2006-02-26 08:36:57 +00:00
Evan Cheng
026fd6af96 Added an offset field to ConstantPoolSDNode. 
llvm-svn: 26371
 2006-02-25 09:54:52 +00:00
Chris Lattner
22356863a0 Pass all the flags to the asm printer, not just the # operands. 
llvm-svn: 26362
 2006-02-24 19:50:58 +00:00
Chris Lattner
f1e0c1f0a8 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. 
Add support for addressing modes.

llvm-svn: 26361
 2006-02-24 19:18:20 +00:00
Chris Lattner
e00cf77ecb Refactor operand adding out to a new AddOperand method 
llvm-svn: 26358
 2006-02-24 18:54:03 +00:00
Jeff Cohen
9773f9c447 Get VC++ building again. 
llvm-svn: 26351
 2006-02-24 02:52:40 +00:00
Chris Lattner
6248339a24 Implement (most of) selection of inline asm memory operands. 
llvm-svn: 26350
 2006-02-24 02:13:54 +00:00
Chris Lattner
3f267c1683 Lower C_Memory operands. 
llvm-svn: 26346
 2006-02-24 01:11:24 +00:00
Chris Lattner
5a70e894d1 Fix an endianness problem on big-endian targets with expanded operands 
to inline asms.  Mark some methods const.

llvm-svn: 26334
 2006-02-23 20:06:57 +00:00
Chris Lattner
b4951fbe82 Record all of the expanded registers in the DAG and machine instr, fixing 
several bugs in inline asm expanded operands.

llvm-svn: 26332
 2006-02-23 19:21:04 +00:00
Chris Lattner
2fc133f091 This fixes a couple of problems with expansion 
llvm-svn: 26318
 2006-02-22 23:09:03 +00:00
Chris Lattner
d1886b8a4e Change a whole bunch of code to be built around RegsForValue instead of 
a single register number.  This fully implements promotion for inline asms,
expand is close but not quite right yet.

llvm-svn: 26316
 2006-02-22 22:37:12 +00:00
Chris Lattner
6bb2c3e9cd split register class handling from explicit physreg handling. 
llvm-svn: 26308
 2006-02-22 00:56:39 +00:00
Chris Lattner
b5b7cc99c4 Adjust to changes in getRegForInlineAsmConstraint prototype 
llvm-svn: 26306
 2006-02-21 23:12:12 +00:00
Chris Lattner
4b5130d957 Fix a problem Nate and Duraid reported where simplifying nodes can cause 
them to get ressurected, in which case, deleting the undead nodes is
unfriendly.

llvm-svn: 26291
 2006-02-20 06:51:04 +00:00
Chris Lattner
d5b8bfef65 Fix a problem on itanium with memset. The value to set has been promoted to 
i64 before this code, so zero_ext doesn't work.

llvm-svn: 26290
 2006-02-20 06:38:35 +00:00
Nate Begeman
bbcae2bf3d Add checks to make sure we don't create bogus extend nodes, and fix a bug 
where we were doing exactly that which was causing failures on x86 and
alpha.

llvm-svn: 26284
 2006-02-18 02:40:58 +00:00
Chris Lattner
bd36f029ef Fix a tricky issue in the SimplifyDemandedBits code where CombineTo wasn't 
exactly the API we wanted to call into.  This fixes the crash on crafty last
night.

llvm-svn: 26269
 2006-02-17 21:58:01 +00:00
Nate Begeman
7ebd8fd80d Clean up DemandedBitsAreZero interface 
Make more use of the new mask helpers in valuetypes.h
Combine (sra (srl x, c1), c1) -> sext_inreg if legal

llvm-svn: 26263
 2006-02-17 19:54:08 +00:00
Nate Begeman
a3a0a0340f Don't expand sdiv by power of two before legalize, since it will likely 
generate illegal nodes.

llvm-svn: 26261
 2006-02-17 07:26:20 +00:00
Nate Begeman
9c0ab71f4a kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
 2006-02-17 05:43:56 +00:00
Chris Lattner
6632b8ab04 Fix another miscompilation exposed by lencode, where we lowered i64->f32 
conversions to __floatdidf instead of __floatdisf on targets that support
f32 but not i64 (e.g. sparc).

llvm-svn: 26254
 2006-02-17 04:32:33 +00:00
Evan Cheng
a2433f32b4 Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it 
turns out not to point to a constant string but it forgot change the offset
back.

llvm-svn: 26242
 2006-02-16 23:11:42 +00:00
Nate Begeman
0bc71999b9 Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238
 2006-02-16 21:11:51 +00:00
Evan Cheng
131901cbb8 If the false case is the current basic block, then this is a self loop. 
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.

llvm-svn: 26231
 2006-02-16 08:27:56 +00:00
Chris Lattner
6f407a54c1 Lowering of sdiv X, pow2 was broken, this fixes it. This patch is written 
by Nate, I'm just committing it for him.

llvm-svn: 26230
 2006-02-16 08:02:36 +00:00
Evan Cheng
07063456aa Remove an unused function parameter. 
llvm-svn: 26221
 2006-02-15 22:12:35 +00:00
Evan Cheng
5c2ecfd29b Turn a memcpy from string constant into a series of stores of constant values. 
llvm-svn: 26219
 2006-02-15 21:59:04 +00:00
Jim Laskey
e51152ac31 Should not combine ISD::LOCATIONs until we have scheme to remove from 
MachineDebugInfo tables.

llvm-svn: 26216
 2006-02-15 19:34:44 +00:00
Evan Cheng
3f9201ab48 Lower memcpy with small constant size operand into a series of load / store 
ops.

llvm-svn: 26195
 2006-02-15 01:54:51 +00:00
Evan Cheng
6789a748ac Doh again! 
llvm-svn: 26188
 2006-02-14 23:05:54 +00:00
Evan Cheng
5a2a9d3896 Keep to < 80 cols 
llvm-svn: 26177
 2006-02-14 20:12:38 +00:00