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1832 Commits

Author SHA1 Message Date
Evan Cheng
1a06b12330 Use ldr.n to workaround a darwin assembler bug. 
llvm-svn: 85980
 2009-11-04 00:00:39 +00:00
Evan Cheng
b50510c510 Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long. 
llvm-svn: 85965
 2009-11-03 23:13:34 +00:00
Evan Cheng
caab17007b fconsts / fconstd immediate should be proceeded with #. 
llvm-svn: 85952
 2009-11-03 21:59:33 +00:00
Anton Korobeynikov
de7cbab064 Move subtarget check upper for NEON reg-reg fixup pass. 
llvm-svn: 85914
 2009-11-03 18:46:11 +00:00
Evan Cheng
1d4575274c Trim unnecessary include. 
llvm-svn: 85878
 2009-11-03 07:08:08 +00:00
Bob Wilson
97331f70ca For Thumb indirect branches, use "mov pc, reg" which does not switch 
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874
 2009-11-03 06:29:56 +00:00
Evan Cheng
ed22395c61 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
llvm-svn: 85871
 2009-11-03 05:52:54 +00:00
Evan Cheng
2807af42c0 Clean up copyRegToReg. 
llvm-svn: 85870
 2009-11-03 05:51:39 +00:00
Evan Cheng
9bedf1b587 Add QPR_8 as a superreg class of SPR_8 and DPR_8. 
llvm-svn: 85869
 2009-11-03 05:50:57 +00:00
Ted Kremenek
a474928cda Update CMake file. 
llvm-svn: 85861
 2009-11-03 04:14:12 +00:00
Anton Korobeynikov
ff29071cc6 Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time. 
llvm-svn: 85850
 2009-11-03 01:04:26 +00:00
Anton Korobeynikov
48b30c79be Revert r85049, it is causing PR5367 
llvm-svn: 85847
 2009-11-03 00:24:48 +00:00
Bob Wilson
7e071e14eb Revert previous change to a comment. The BlockAddresses go in the 
constant pool so they don't get wrapped separately.

llvm-svn: 85844
 2009-11-03 00:02:05 +00:00
Bob Wilson
3144715b53 Put BlockAddresses into ARM constant pools. 
llvm-svn: 85824
 2009-11-02 20:59:23 +00:00
Kevin Enderby
633b294095 Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should 
have been passed as a reference.

llvm-svn: 85823
 2009-11-02 20:14:39 +00:00
David Goodwin
9aa890eab6 Fix schedule model for BFC. 
llvm-svn: 85809
 2009-11-02 17:28:36 +00:00
Bob Wilson
0c213bed8b Hyphenate some comments. 
llvm-svn: 85808
 2009-11-02 17:10:37 +00:00
Bob Wilson
6eb4f53d90 Add support for BlockAddress values in ARM constant pools. 
llvm-svn: 85806
 2009-11-02 16:59:06 +00:00
Bob Wilson
ac53e0c640 Prune unnecessary include. 
llvm-svn: 85805
 2009-11-02 16:58:31 +00:00
Evan Cheng
e79ff8a615 These are done / no longer care. 
llvm-svn: 85798
 2009-11-02 07:58:25 +00:00
Evan Cheng
532dfd431f Add an entry. 
llvm-svn: 85797
 2009-11-02 07:51:19 +00:00
Evan Cheng
57f7c7c914 Unbreak ARMBaseRegisterInfo::copyRegToReg. 
llvm-svn: 85787
 2009-11-02 04:44:55 +00:00
Anton Korobeynikov
09147da530 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
llvm-svn: 85767
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
9737bfedeb Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
 2009-11-02 00:11:39 +00:00
Anton Korobeynikov
ed410a8ee3 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
llvm-svn: 85765
 2009-11-02 00:11:06 +00:00
Anton Korobeynikov
3ba3789153 Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) 
llvm-svn: 85764
 2009-11-02 00:10:38 +00:00
Evan Cheng
a409c074c8 Fix a couple more places where we are creating ld / st instructions without memoperands. 
llvm-svn: 85746
 2009-11-01 22:04:35 +00:00
Evan Cheng
4a0d47f209 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
llvm-svn: 85743
 2009-11-01 21:12:51 +00:00
Evan Cheng
de16fff3e8 Use cbz and cbnz instructions. 
llvm-svn: 85698
 2009-10-31 23:46:45 +00:00
Jim Grosbach
5b094f3b36 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

llvm-svn: 85697
 2009-10-31 22:57:36 +00:00
Jim Grosbach
ace75c4288 Expand 64-bit logical shift right inline 
llvm-svn: 85687
 2009-10-31 21:42:19 +00:00
Jim Grosbach
16ae289667 Expand 64-bit arithmetic shift right inline 
llvm-svn: 85685
 2009-10-31 21:00:56 +00:00
Jim Grosbach
534d2cb249 Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675
 2009-10-31 19:38:01 +00:00
Evan Cheng
9178904e56 It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. 
llvm-svn: 85643
 2009-10-31 03:39:36 +00:00
Kevin Enderby
c8d047130a Updates to the ARM target assembler for llvm-mc per review comments from 
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.

llvm-svn: 85632
 2009-10-30 22:55:57 +00:00
Bob Wilson
1c2cbe3945 Add a note about Robert Muth's alternate jump table implementation. 
llvm-svn: 85624
 2009-10-30 22:22:46 +00:00
Bob Wilson
94d79c1f43 Fix a comment. 
llvm-svn: 85610
 2009-10-30 20:13:25 +00:00
Rafael Espindola
d4fadd76da This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590
 2009-10-30 14:33:14 +00:00
Bob Wilson
95064e348a Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577
 2009-10-30 05:45:42 +00:00
Jim Grosbach
95e1ff2dba Dial back the realignment a bit. 
llvm-svn: 85546
 2009-10-30 00:08:40 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Jim Grosbach
071b4ec891 To get more thorough testing from llc-beta nightly runs, do dynamic stack 
realignment regardless of whether it's strictly necessary.

llvm-svn: 85476
 2009-10-29 02:41:21 +00:00
Bob Wilson
fc1194919b Revert r85346 change to control tail merging by CodeGenOpt::Level. 
I'm going to redo this using the OptimizeForSize function attribute.

llvm-svn: 85426
 2009-10-28 20:46:46 +00:00
Bob Wilson
af37728221 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411
 2009-10-28 18:26:41 +00:00
Evan Cheng
519b231883 fconsts and fconstd are obviously re-materializable. 
llvm-svn: 85410
 2009-10-28 18:19:56 +00:00
Jim Grosbach
e42dc83a9f Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2. 
llvm-svn: 85406
 2009-10-28 17:33:28 +00:00
Evan Cheng
16ed5ac7ff Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. 
llvm-svn: 85381
 2009-10-28 06:55:03 +00:00
Evan Cheng
1babe43881 Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Bob Wilson
b709aa6b3c Add an indirect branch pattern for ARM. Testcase will be coming soon. 
llvm-svn: 85355
 2009-10-28 00:37:03 +00:00
Bob Wilson
98c9fb94ab Record CodeGen optimization level in the BranchFolding pass so that we can 
use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346
 2009-10-27 23:49:38 +00:00