1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Commit Graph

91483 Commits

Author SHA1 Message Date
Adrian Prantl
1a2b6a92ae Bugfix for the debug intrinsic handling in InstCombiner:
Since we can't guarantee that the original dbg.declare instrinsic
is removed by LowerDbgDeclare(), we need to make sure that we are
not inserting the same dbg.value intrinsic over and over.
This removes tons of redundant DIEs when compiling optimized code.

rdar://problem/13056109

llvm-svn: 180615
2013-04-26 17:48:33 +00:00
Ulrich Weigand
192ae78a10 PowerPC: Use RegisterOperand instead of RegisterClass operands
In the default PowerPC assembler syntax, registers are specified simply
by number, so they cannot be distinguished from immediate values (without
looking at the opcode).  This means that the default operand matching logic
for the asm parser does not work, and we need to specify custom matchers.
Since those can only be specified with RegisterOperand classes and not
directly on the RegisterClass, all instructions patterns used by the asm
parser need to use a RegisterOperand (instead of a RegisterClass) for
all their register operands.

This patch adds one RegisterOperand for each RegisterClass, using the
same name as the class, just in lower case, and updates all instruction
patterns to use RegisterOperand instead of RegisterClass operands.

llvm-svn: 180611
2013-04-26 16:53:15 +00:00
Silviu Baranga
4e4dc8ed27 Re-write the address propagation code for pre-indexed loads/stores to take into account some previously misssed cases (PRE_DEC addressing mode, the offset and base address are swapped, etc). This should fix PR15581.
llvm-svn: 180609
2013-04-26 15:52:24 +00:00
Ulrich Weigand
edc2de8f08 PowerPC: Fix encoding of vsubcuw and vsum4sbs instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong sub-opcodes).

Tests will be added together with the asm parser.

llvm-svn: 180608
2013-04-26 15:39:57 +00:00
Ulrich Weigand
ad315c6b60 PowerPC: Fix encoding of stfsu and stfdu instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong sub-opcodes).  Note that apparently
the compiler currently never generates pre-inc instructions
for floating point types for some reason ...

Tests will be added together with the asm parser.

llvm-svn: 180607
2013-04-26 15:39:40 +00:00
Ulrich Weigand
71ccd2df46 PowerPC: Fix encoding of rldimi and rldcl instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong operand name in rldimi, wrong form
and sub-opcode for rldcl).

Tests will be added together with the asm parser.

llvm-svn: 180606
2013-04-26 15:39:12 +00:00
Ulrich Weigand
9121e6ec8f PowerPC: Support PC-relative fixup_ppc_brcond14.
When testing the asm parser, I ran into an error when using a conditional
branch to an external symbol (this doesn't occur in compiler-generated
code) due to missing support in PPCELFObjectWriter::getRelocTypeInner.

llvm-svn: 180605
2013-04-26 15:38:30 +00:00
Benjamin Kramer
40a2d53c85 ARM/NEON: Pattern match vector integer abs to vabs.
llvm-svn: 180604
2013-04-26 15:00:57 +00:00
Benjamin Kramer
11723aa321 X86: Now that we have a canonical form for vector integer abs, match it into pabs.
llvm-svn: 180600
2013-04-26 12:05:21 +00:00
Benjamin Kramer
7ce75fb032 DAGCombiner: Canonicalize vector integer abs in the same way we do it for scalars.
This already helps SSE2 x86 a lot because it lacks an efficient way to
represent a vector select. The long term goal is to enable the backend to match
a canonicalized pattern into a single instruction (e.g. vabs or pabs).

llvm-svn: 180597
2013-04-26 09:19:19 +00:00
Nadav Rotem
fe6c769d60 LoopVectorizer: Calculate the number of pointers to disambiguate at runtime based on the numbers of reads and writes.
llvm-svn: 180593
2013-04-26 05:08:59 +00:00
Michael Gottesman
2188c467aa Use 'git svn find-rev' in git-svnrevert instead of shell script fu.
Thanks Chandler!

llvm-svn: 180592
2013-04-26 03:27:39 +00:00
Michael Gottesman
9bb33b83ef Revert "[objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls that were once autoreleaseRV instructions."
This reverts commit r180222.

I think this might tie in with a different problem which will require a
different approach potentially. I am reverting this in the case I need to go
down that second path.

My apologies for the noise. = /.

llvm-svn: 180590
2013-04-26 01:12:18 +00:00
Michael Gottesman
4f7b7f0655 Updated GettingStarted.rst so that it references utils/git-svn for git-svnup instead of catting it into the documentation itself.
llvm-svn: 180589
2013-04-26 01:04:45 +00:00
Michael Gottesman
27f2ffe478 Added the scripts git-svnup/git-svnrevert to utils/git-svn.
It makes more sense to have git-svnup here than catting said file in the
documentation (where we should rather point users to this directory).
I included git-svnrevert as an additional gift to the community. I will update
the documentation in a second commit later today.

git-svnrevert takes in a git hash for a commit, looks up the svn revision for
said commit and then creates the normal git revert commit message with the one
liner message, except instead of saying

  Revert "<<<INSERT ONELINER HERE>>>"

  This reverts commit <<<INSERT GITHASH HERE>>>

It says:

  Revert "<<<INSERT ONELINER HERE>>>"

  This reverts commit r<<<INSERT SVN REVISION HERE>>>

so git hashes will not escape into our svn logs (which just look unseemly).

llvm-svn: 180587
2013-04-26 00:58:45 +00:00
Jack Carter
02ade2a6d8 Mips assembler: .set reorder support
Mips have delayslots for certain instructions 
like jumps and branches. These are instructions 
that follow the branch or jump and are executed
before the jump or branch is completed.

Early Mips compilers could not cope with delayslots
and left them up to the assembler. The assembler would
fill the delayslots with the appropriate instruction,
usually just a nop to allow correct runtime behavior.

The default behavior for this is set with .set reorder.
To tell the assembler that you don't want it to mess with
the delayslot one used .set noreorder.

For backwards compatibility we need to support
.set reorder and have it be the default behavior in the 
assembler.

Our support for it is to insert a NOP directly after an
instruction with a delayslot when in .set reorder mode.

Contributer: Vladimir Medic
llvm-svn: 180584
2013-04-25 23:31:35 +00:00
Michael Liao
4cd6523c9e Remove SMLoc paired with CHECK-NOT patterns. Not functionality change.
Pattern has source location by itself. After adding a trivial method to
retrieve it, it's unnecessary to pair a source location for CHECK-NOT patterns.
One thing revised after this is the diagnostic info is more accurate by
pointing to the start of the CHECK-NOT pattern instead of the end of the
CHECK-NOT pattern. E.g. diagnostic message previously looks like

    <stdin>:1:1: error: CHECK-NOT: string occurred!
    test
    ^
    test.txt:1:16: note: CHECK-NOT: pattern specified here
    CHECK-NOT: test
                   ^

is changed to

    <stdin>:1:1: error: CHECK-NOT: string occurred!
    test
    ^
    test.txt:1:12: note: CHECK-NOT: pattern specified here
    CHECK-NOT: test
               ^

llvm-svn: 180578
2013-04-25 21:31:34 +00:00
Preston Gurd
f91db4a8a0 Make function documentation conform to llvm standards.
Expunge all remaining traces and use of live variable information.

llvm-svn: 180577
2013-04-25 21:31:33 +00:00
Arnold Schwaighofer
b1fc314b5f ARM cost model: Integer div and rem is lowered to a function call
Reflect this in the cost model. I observed this in MiBench/consumer-lame.

radar://13354716

llvm-svn: 180576
2013-04-25 21:16:18 +00:00
Andrew Kaylor
b5c81265a9 Re-enabling MCJIT object caching with memory leak fixed
llvm-svn: 180575
2013-04-25 21:02:36 +00:00
Chris Lattner
49248bb367 revert r179735, it has no testcases, and doesn't really make sense.
llvm-svn: 180574
2013-04-25 20:34:16 +00:00
Preston Gurd
0547d81fdb This patch adds the X86FixupLEAs pass, which will reduce instruction
latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is both
useful and possible to do so.

llvm-svn: 180573
2013-04-25 20:29:37 +00:00
Nadav Rotem
d5eaf768a9 LoopVectorizer: No need to generate pointer disambiguation checks between readonly pointers.
llvm-svn: 180570
2013-04-25 19:55:03 +00:00
Reid Kleckner
9efd3d0aa0 [mc-coff] Forward Linker Option flags into the .drectve section
Summary:
This is modelled on the Mach-O linker options implementation and should
support a Clang implementation of #pragma comment(lib/linker).

Reviewers: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D724

llvm-svn: 180569
2013-04-25 19:34:41 +00:00
Rafael Espindola
e426e8360c Fix section relocation for SECTIONREL32 with immediate offset.
Patch by Kai Nacke. This matches the gnu as output.

llvm-svn: 180568
2013-04-25 19:27:05 +00:00
Michael Liao
66349b434b Remove tailing whitespaces
llvm-svn: 180564
2013-04-25 18:54:02 +00:00
Chad Rosier
3030f76a0d [inline asm] Add a test case for r180226. The specific issue is that the inline
assembly is requesting a 64-bit register, which is invalid for i386.
rdar://13731657

llvm-svn: 180445
2013-04-25 17:10:21 +00:00
Rafael Espindola
716067bf18 Use a pointer as the relocation iterator.
Since the relocation iterator walks only the relocations in one section, we
can just use a pointer and avoid fetching information about the section at
every reference.

llvm-svn: 180262
2013-04-25 12:45:46 +00:00
Rafael Espindola
9541db893e Clarify getRelocationAddress x getRelocationOffset a bit.
getRelocationAddress is for dynamic libraries and executables,
getRelocationOffset for relocatable objects.

Mark the getRelocationAddress of COFF and MachO as not implemented yet. Add a
test of ELF's. llvm-readobj -r now prints the same values as readelf -r.

llvm-svn: 180259
2013-04-25 12:28:45 +00:00
Silviu Baranga
c656dd9bdd Fix constant folding for one lane vector types. Constant folding one lane vector types not returns a vector instead of a scalar.
llvm-svn: 180254
2013-04-25 09:32:33 +00:00
Rafael Espindola
d89ddc118c Revert "Adding object caching support to MCJIT"
This reverts commit 07f03923137a91e3cca5d7fc075a22f8c9baf33a.

Looks like it broke the valgrind bot:

http://lab.llvm.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/649

llvm-svn: 180249
2013-04-25 03:47:41 +00:00
Rafael Espindola
ec78b42518 Revert "Exposing MCJIT through C API"
This reverts commit 8c31b298149ca3c3f2bbd9e8aa9a01c4d91f3d74.

It looks like this commit broke some bots:

http://lab.llvm.org:8011/builders/llvm-ppc64-linux2/builds/5209

llvm-svn: 180248
2013-04-25 03:19:12 +00:00
Rafael Espindola
8636f5cbc3 Don't compute a std::vector<uint8_t> just to write it out a stream.
llvm-svn: 180247
2013-04-25 03:07:42 +00:00
Akira Hatanaka
1eb1207ce9 Test case for r180241.
llvm-svn: 180246
2013-04-25 02:22:07 +00:00
Akira Hatanaka
b42fb2ad92 Test case for r180238.
llvm-svn: 180245
2013-04-25 02:21:09 +00:00
Akira Hatanaka
587ba11650 [mips] Add definitions of micromips load and store instructions.
Patch by Zoran Jovanovic.

llvm-svn: 180241
2013-04-25 01:21:25 +00:00
Filipe Cabecinhas
361c89c281 Allow users to choose identity used to sign tools.
Summary:
No change if the identity isn't defined by the makefile.

Reviewers: echristo

Differential Revision: http://llvm-reviews.chandlerc.com/D632

llvm-svn: 180240
2013-04-25 01:17:54 +00:00
Akira Hatanaka
fd15a7b67e [mips] Add definitions of micromips shift instructions.
Patch by Zoran Jovanovic.

llvm-svn: 180238
2013-04-25 01:11:15 +00:00
Andrew Kaylor
be18a2273e Fixing OCAML bindings for MCJIT
llvm-svn: 180232
2013-04-25 00:03:58 +00:00
Tom Stellard
222f7ab2fb R600: Initialize BooleanVectorContents
Fixes test/CodeGen/R600/setcc.ll

llvm-svn: 180231
2013-04-24 23:56:18 +00:00
Tom Stellard
48d161332e R600: Use SHT_PROGBITS for the .AMDGPU.config section
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

llvm-svn: 180230
2013-04-24 23:56:14 +00:00
Andrew Kaylor
57cfdd1d3d Exposing MCJIT through C API
Patch by Filip Pizlo

llvm-svn: 180229
2013-04-24 23:33:53 +00:00
Andrew Trick
378cafade4 Fix for r180193 - MI Sched: eliminate local vreg.
Fixes PR15838. Need to check for blocks with nothing but dbg.value.

I'm not sure how to force this situation with a unit test. I tried to
reduce the test case in PR15838 (1k lines of metadata) but gave up.

llvm-svn: 180227
2013-04-24 23:19:56 +00:00
Chad Rosier
f4418505b3 [inline asm] Fix a crasher for an invalid value type/register class.
rdar://13731657

llvm-svn: 180226
2013-04-24 22:53:10 +00:00
Andrew Kaylor
4911adbdfd Making invalidateInstructionCache automatic in SectionMemoryManager
llvm-svn: 180225
2013-04-24 22:39:12 +00:00
Michael Gottesman
0c2ffd01ef [objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls that were once autoreleaseRV instructions.
Due to the semantics of ARC, we must be extremely conservative with autorelease
calls inserted by the frontend since ARC gaurantees that said object will be in
the autorelease pool after that point, an optimization invariant that the
optimizer must respect.

On the other hand, we are allowed significantly more flexibility with
autoreleaseRV instructions.

Often times though this flexibility is disrupted by early transformations which
transform objc_autoreleaseRV => objc_autorelease if said instruction is no
longer being used as part of an RV pair (generally due to inlining). Since we
can not tell the difference in between an autorelease put into place by the
frontend and one created through said ``strength reduction'' we can not perform
these optimizations.

The addition of this set gets around said issues by allowing us to differentiate
in between said two cases.

rdar://problem/13697741.

llvm-svn: 180222
2013-04-24 22:18:18 +00:00
Michael Gottesman
6edf0d6d80 Fixed comment typo.
llvm-svn: 180221
2013-04-24 22:18:15 +00:00
Jack Carter
3fa12e632e Mips assembler: Add 64 bit testing for JAL
Contributer: Vladimir Medic
llvm-svn: 180220
2013-04-24 21:52:42 +00:00
Rafael Espindola
9e7ded9509 Use pointers to iterate over symbols.
While here, don't report a dummy symbol for relocations that don't have symbols.
We used to says such relocations were for the first defined symbol, but now we
return end_symbols(). The llvm-readobj output change agrees with otool.

llvm-svn: 180214
2013-04-24 19:47:55 +00:00
Rafael Espindola
372ed9c7fd Don't produce an empty llvm.compiler.used in LTO.
LTO was always creating an empty llvm.compiler.used. With this patch we
now first check if there is anything to be added first.

Unfortunately, there is no good way to test libLTO in isolation as it needs gold
or ld64, but there are bots doing LTO builds that found this problem.

llvm-svn: 180202
2013-04-24 17:54:35 +00:00