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24450 Commits

Author SHA1 Message Date
Evan Cheng
1c010771f4 Cortex-R5 can issue Thumb2 integer division instructions. 
llvm-svn: 183275
 2013-06-04 22:52:09 +00:00
Arnold Schwaighofer
59cf81c2e1 Revert series of sched model patches until I figure out what is going on. 
llvm-svn: 183273
 2013-06-04 22:35:17 +00:00
Arnold Schwaighofer
d787aba409 ARM sched model: Add VFP div instruction on Swift 
llvm-svn: 183271
 2013-06-04 22:16:08 +00:00
Arnold Schwaighofer
1078009cb6 ARM sched model: Add SIMD/VFP load/store instructions on Swift 
llvm-svn: 183270
 2013-06-04 22:16:07 +00:00
Arnold Schwaighofer
bb0c6ae8d0 ARM sched model: Add integer VFP/SIMD instructions on Swift 
llvm-svn: 183269
 2013-06-04 22:16:05 +00:00
Arnold Schwaighofer
0f39267e23 ARM sched model: Add integer load/store instructions on Swift 
llvm-svn: 183268
 2013-06-04 22:16:04 +00:00
Arnold Schwaighofer
19192c53f2 ARM sched model: Add integer arithmetic instructions on Swift 
llvm-svn: 183267
 2013-06-04 22:16:02 +00:00
Arnold Schwaighofer
0266140e21 ARM sched model: Cortex A9 - More InstRW sched resources 
Add more InstRW mappings.

llvm-svn: 183266
 2013-06-04 22:16:00 +00:00
Arnold Schwaighofer
c51f106173 ARM sched model: Add branch thumb instructions 
llvm-svn: 183265
 2013-06-04 22:15:59 +00:00
Arnold Schwaighofer
11f0806b48 ARM sched model: Add branch thumb2 instructions 
llvm-svn: 183264
 2013-06-04 22:15:57 +00:00
Arnold Schwaighofer
f1db24e509 ARM sched model: Add branch instructions 
llvm-svn: 183263
 2013-06-04 22:15:56 +00:00
Arnold Schwaighofer
c552774669 ARM sched model: Add preload thumb2 instructions 
llvm-svn: 183262
 2013-06-04 22:15:54 +00:00
Arnold Schwaighofer
38168a47d6 ARM sched model: Add preload instructions 
llvm-svn: 183261
 2013-06-04 22:15:52 +00:00
Arnold Schwaighofer
555055dd98 ARM sched model: Add more ALU and CMP thumb instructions 
llvm-svn: 183260
 2013-06-04 22:15:51 +00:00
Arnold Schwaighofer
02a38a8742 ARM sched model: Add more ALU and CMP thumb2 instructions 
llvm-svn: 183259
 2013-06-04 22:15:49 +00:00
Arnold Schwaighofer
009aa16396 ARM sched model: Add more ALU and CMP instructions 
llvm-svn: 183258
 2013-06-04 22:15:47 +00:00
Arnold Schwaighofer
fe141a11f4 ARM sched model: Add divsion, loads, branches, vfp cvt 
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

llvm-svn: 183257
 2013-06-04 22:15:46 +00:00
Arnold Schwaighofer
81440608f7 ARMInstrInfo: Improve isSwiftFastImmShift 
An instruction with less than 3 inputs is trivially a fast immediate shift.

llvm-svn: 183256
 2013-06-04 22:15:43 +00:00
Venkatraman Govindaraju
a65d380b15 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
llvm-svn: 183243
 2013-06-04 18:33:25 +00:00
David Majnemer
d0dc0d58f6 ARM: Fix crash in ARM backend inside of ARMConstantIslandPass 
The ARM backend did not expect LDRBi12 to hold a constant pool operand.
Allow for LLVM to deal with the instruction similar to how it deals with
LDRi12.

This fixes PR16215.

llvm-svn: 183238
 2013-06-04 17:46:15 +00:00
Vincent Lejeune
8d2ef79cb9 R600: Swizzle texture/export instructions 
llvm-svn: 183229
 2013-06-04 15:04:53 +00:00
Vladimir Medic
de3118ad1c Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp. 
llvm-svn: 183215
 2013-06-04 08:28:53 +00:00
Aaron Ballman
c198459ea4 Silencing an MSVC warning about mixing bool and unsigned int. 
llvm-svn: 183176
 2013-06-04 01:03:03 +00:00
Tom Stellard
0c2bbb2a1f R600/SI: Add support for work item and work group intrinsics 
llvm-svn: 183138
 2013-06-03 17:40:18 +00:00
Tom Stellard
0faf53682e R600/SI: Add a calling convention for compute shaders 
llvm-svn: 183137
 2013-06-03 17:40:11 +00:00
Tom Stellard
47a52f3e69 R600/SI: Custom lower i64 sign_extend 
llvm-svn: 183136
 2013-06-03 17:40:03 +00:00
Tom Stellard
c08ab0862e R600/SI: Adjust some instructions' out register class after ISel 
This is necessary to avoid generating VGPR to SGPR copies in some
cases.

llvm-svn: 183135
 2013-06-03 17:39:58 +00:00
Tom Stellard
29284f6cc9 R600/SI: Handle REG_SEQUENCE in fitsRegClass() 
llvm-svn: 183134
 2013-06-03 17:39:54 +00:00
Tom Stellard
45c3f3e363 R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands() 
llvm-svn: 183133
 2013-06-03 17:39:50 +00:00
Tom Stellard
d58c6099f1 R600/SI: Fixup CopyToReg register class in PostprocessISelDAG() 
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR.  This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else.  The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.

llvm-svn: 183132
 2013-06-03 17:39:46 +00:00
Tom Stellard
7e44e13b15 R600/SI: Add support for global loads 
llvm-svn: 183131
 2013-06-03 17:39:43 +00:00
Tom Stellard
8e0ca8c4b9 R600/SI: Rework MUBUF store instructions 
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

llvm-svn: 183130
 2013-06-03 17:39:37 +00:00
Vincent Lejeune
991eb7f653 R600: 3 op instructions have no write bit but the result are store in PV 
llvm-svn: 183111
 2013-06-03 15:56:12 +00:00
Vincent Lejeune
97b4286f95 R600: CALL_FS consumes a stack size entry 
llvm-svn: 183108
 2013-06-03 15:44:42 +00:00
Vincent Lejeune
55871f8f8a R600: use capital letter for PV channel 
llvm-svn: 183107
 2013-06-03 15:44:35 +00:00
Vincent Lejeune
66af4ee12a R600: Constraints input regs of interp_xy,_zw 
llvm-svn: 183106
 2013-06-03 15:44:16 +00:00
Ahmed Bougacha
581578b651 X86: sub_xmm registers are 128 bits wide. 
llvm-svn: 183103
 2013-06-03 14:42:40 +00:00
Venkatraman Govindaraju
2d5d39937e Sparc: Add support for indirect branch and blockaddress in Sparc backend. 
llvm-svn: 183094
 2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju
b47bd839e0 Sparc: When storing 0, use %g0 directly in the store instruction instead of 
using two instructions (sethi and store).

llvm-svn: 183090
 2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju
0514a4c845 Sparc: Combine add/or/sethi instruction with restore if possible. 
llvm-svn: 183088
 2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju
acb910b7ae Sparc: Perform leaf procedure optimization by default 
llvm-svn: 183083
 2013-06-02 02:24:27 +00:00
Venkatraman Govindaraju
2425aef2ad Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions. 
llvm-svn: 183079
 2013-06-01 20:42:48 +00:00
Tim Northover
e84e621d63 Revert r183069: "TMP: LEA64_32r fixing" 
Very sorry, it was committed from the wrong branch by mistake.

llvm-svn: 183070
 2013-06-01 10:23:46 +00:00
Tim Northover
93287c3991 TMP: LEA64_32r fixing 
llvm-svn: 183069
 2013-06-01 10:21:54 +00:00
Tim Northover
8efc0e4868 X86: change MOV64ri64i32 into MOV32ri64 
The MOV64ri64i32 instruction required hacky MCInst lowering because it
was allocated as setting a GR64, but the eventual instruction ("movl")
only set a GR32. This converts it into a so-called "MOV32ri64" which
still accepts a (appropriate) 64-bit immediate but defines a GR32.
This is then converted to the full GR64 by a SUBREG_TO_REG operation,
thus keeping everyone happy.

This fixes a typo in the opcode field of the original patch, which
should make the legact JIT work again (& adds test for that problem).

llvm-svn: 183068
 2013-06-01 09:55:14 +00:00
Venkatraman Govindaraju
1eaf496598 [Sparc] Generate correct code for leaf functions with stack objects 
llvm-svn: 183067
 2013-06-01 04:51:18 +00:00
Ahmed Bougacha
2263547c8f Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061
 2013-05-31 23:45:26 +00:00
Eric Christopher
e4ab862999 Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as it 
seems to have caused PR16192 and other JIT related failures.

llvm-svn: 183059
 2013-05-31 23:30:45 +00:00
Benjamin Kramer
c60747c08c NVPTX: Don't even create a regalloc if we're not going to use it. 
Fixes a leak found by valgrind.

llvm-svn: 183031
 2013-05-31 19:21:58 +00:00
Ahmed Bougacha
5df932894e Add a way to define the bit range covered by a SubRegIndex. 
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.

In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.

llvm-svn: 183020
 2013-05-31 17:08:36 +00:00