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1c3ea75ffc
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174 Commits

Author SHA1 Message Date
Evan Cheng
1c3ea75ffc Added X86 readport patterns. 
llvm-svn: 24879
 2005-12-20 07:38:38 +00:00
Evan Cheng
bb34a50cb0 X86 conditional branch support. 
llvm-svn: 24870
 2005-12-19 23:12:38 +00:00
Chris Lattner
399dfec939 eliminate some redundancy 
llvm-svn: 24781
 2005-12-17 19:47:05 +00:00
Evan Cheng
6a94c77c55 Added anyext, modelled as zext on X86. 
llvm-svn: 24759
 2005-12-17 01:47:57 +00:00
Evan Cheng
5d90b26707 Added support for cmp, test, and conditional move instructions. 
llvm-svn: 24756
 2005-12-17 01:24:02 +00:00
Evan Cheng
43152cb8b6 * Promote all 1 bit entities to 8 bit. 
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726
 2005-12-15 19:49:23 +00:00
Evan Cheng
f72e7055c0 Added frameindex, constpool, globaladdr, and externalsym as root nodes of 
leaaddr.

llvm-svn: 24724
 2005-12-15 08:31:04 +00:00
Evan Cheng
576b826f71 Use MOV8rm to load 1 bit value. 
llvm-svn: 24721
 2005-12-15 00:59:17 +00:00
Evan Cheng
3b094e89fb Added sext and zext patterns. 
llvm-svn: 24705
 2005-12-14 02:22:27 +00:00
Evan Cheng
ad1e2fd14a Add load + store folding srl and sra patterns. 
llvm-svn: 24696
 2005-12-13 07:24:22 +00:00
Evan Cheng
63f60d3edb Beautify a few patterns. 
llvm-svn: 24690
 2005-12-13 02:40:18 +00:00
Evan Cheng
95d46be9e6 Some shl patterns which do load + store folding. 
llvm-svn: 24689
 2005-12-13 02:34:51 +00:00
Evan Cheng
6beadf1c29 A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. 
llvm-svn: 24688
 2005-12-13 01:57:51 +00:00
Evan Cheng
d233c28d29 Add and, or, and xor patterns which fold load + stores. 
llvm-svn: 24687
 2005-12-13 01:41:36 +00:00
Evan Cheng
62999d6c5d Add inc + dec patterns which fold load + stores. 
llvm-svn: 24686
 2005-12-13 01:02:47 +00:00
Evan Cheng
7f9fb7b095 Add neg and not patterns which fold load + stores. 
llvm-svn: 24685
 2005-12-13 00:54:44 +00:00
Evan Cheng
240071c011 Missed a couple redundant explicit type casts. 
llvm-svn: 24684
 2005-12-13 00:25:07 +00:00
Evan Cheng
e80ec06aaf Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc. 
llvm-svn: 24683
 2005-12-13 00:14:11 +00:00
Evan Cheng
ea7f208813 * Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands. 
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.

llvm-svn: 24682
 2005-12-13 00:01:09 +00:00
Evan Cheng
0ee9dc460a Add some integer mul patterns. 
llvm-svn: 24681
 2005-12-12 23:47:46 +00:00
Evan Cheng
6c9f9ea7ec Add some sub patterns. 
llvm-svn: 24675
 2005-12-12 21:54:05 +00:00
Evan Cheng
145318aefb Add a few more add / store patterns. e.g. ADD32mi8. 
llvm-svn: 24670
 2005-12-12 19:45:23 +00:00
Evan Cheng
56f62789d7 * Added X86 store patterns. 
* Added X86 dec patterns.

llvm-svn: 24654
 2005-12-10 00:48:20 +00:00
Evan Cheng
6610545b7e Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al 
llvm-svn: 24648
 2005-12-09 22:48:48 +00:00
Evan Cheng
6eb25df63a Added explicit type field to ComplexPattern. 
llvm-svn: 24637
 2005-12-08 02:15:07 +00:00
Evan Cheng
1712ee5ab9 * Added intelligence to X86 LEA addressing mode matching routine so it returns 
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.

llvm-svn: 24635
 2005-12-08 02:01:35 +00:00
Evan Cheng
60cc8da341 Remove unnecessary let hasCtrlDep=1 now it can be inferred. 
llvm-svn: 24611
 2005-12-05 23:09:43 +00:00
Chris Lattner
3583f5337b Several things: 
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly.  The port number really
   *is* a 16-bit value, but the patterns should only match if the number
   is 0-255.  Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
   i8, not an i16 as they were believed to be before.  This previous fib
   stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.

llvm-svn: 24599
 2005-12-05 02:40:25 +00:00
Evan Cheng
1ce02890ce Added isel patterns for RET, JMP, and WRITEPORT. 
llvm-svn: 24588
 2005-12-04 08:19:43 +00:00
Evan Cheng
f1352fa7d6 Proper support for shifts with register shift value. 
llvm-svn: 24559
 2005-12-01 00:43:55 +00:00
Nate Begeman
84be54b731 No longer track value types for asm printer operands, and remove them as 
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.

llvm-svn: 24541
 2005-11-30 18:54:35 +00:00
Chris Lattner
fdc786b18f Fix a bug in a recent patch that broke shifts 
llvm-svn: 24526
 2005-11-30 05:11:18 +00:00
Evan Cheng
f412b7ba0c Add more X86 ISel patterns. 
llvm-svn: 24520
 2005-11-29 19:38:52 +00:00
Chris Lattner
5d9ecff961 encode rdtsc correctly 
llvm-svn: 24435
 2005-11-20 22:13:18 +00:00
Andrew Lenharth
a369904fc5 The second patch of X86 support for read cycle counter. 
llvm-svn: 24430
 2005-11-20 21:41:10 +00:00
Chris Lattner
af79013023 Teach the x86 backend about the register constraints of its addressing mode. 
Patch by Evan Cheng

llvm-svn: 24423
 2005-11-19 07:01:30 +00:00
Chris Lattner
72fa26a85b add more patterns, patch by Evan Cheng. 
llvm-svn: 24406
 2005-11-18 01:04:42 +00:00
Chris Lattner
f829636c6b Add patterns for some 16-bit immediate instructions, patch contributed by 
Evan Cheng.

llvm-svn: 24384
 2005-11-17 02:01:55 +00:00
Chris Lattner
fec54e57a0 Add patterns for several simple instructions that take i32 immediates. 
Patch contributed by Evan Cheng!

llvm-svn: 24382
 2005-11-16 22:59:19 +00:00
Nate Begeman
3b6c2df603 Properly split f32 and f64 into separate register classes for scalar sse fp 
fixing a bunch of nasty hackery

llvm-svn: 23735
 2005-10-14 22:06:00 +00:00
Chris Lattner
54139f0b83 give all operands names 
llvm-svn: 23356
 2005-09-14 21:10:24 +00:00
Chris Lattner
d7bd59d77e add a few missing cases 
llvm-svn: 22891
 2005-08-19 00:41:29 +00:00
Chris Lattner
f62a66a21c Give ADJCALLSTACKDOWN/UP the correct operands. 
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.

llvm-svn: 22890
 2005-08-19 00:38:22 +00:00
Nate Begeman
6cd034da8e Scalar SSE: load +0.0 -> xorps/xorpd 
Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted

llvm-svn: 22637
 2005-08-03 23:26:28 +00:00
Nate Begeman
957e0e7c9e Get closer to fully working scalar FP in SSE regs. This gets singlesource 
working, and Olden/power.

llvm-svn: 22441
 2005-07-15 00:38:55 +00:00
Nate Begeman
e5314eb2c2 First round of support for doing scalar FP using the SSE2 ISA extension and 
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340
 2005-07-06 18:59:04 +00:00
Nate Begeman
032a94775d Initial set of .td file changes necessary to get scalar fp in xmm registers 
working.  The instruction selector changes will hopefully be coming later
this week once they are debugged.  This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87.  As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier.  This leads to significantly
better codegen in several cases.

llvm-svn: 22300
 2005-06-27 21:20:31 +00:00
Chris Lattner
7327c042b4 Add markers in the asm file for tail calls, add a new ADJSTACKPTRri 
sorta-pseudo-instruction

llvm-svn: 22042
 2005-05-15 03:10:37 +00:00
Chris Lattner
64232a8480 Yes, calltarget is the operand of the day. 
llvm-svn: 22040
 2005-05-15 01:10:30 +00:00
Chris Lattner
37e226fa9b Add some new instructions 
llvm-svn: 22036
 2005-05-14 23:35:21 +00:00