RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 06:22:56 +02:00
Code Issues Projects Releases Wiki Activity
41,919 Commits 4 Branches 5 Tags 704 MiB
1de8b23129
Commit Graph

41919 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jim Grosbach
1de8b23129 Update the stub and callback code to handle lazy compilation. The stub 
is re-written by the callback to branch directly to the compiled code
in future invocations.

Added back in range-based memory permission functions for the updating of
the stub on Darwin.

llvm-svn: 57846
 2008-10-20 21:39:23 +00:00
Dan Gohman
204cc4e5ff Fast-isel no longer an experiment. 
llvm-svn: 57845
 2008-10-20 21:30:12 +00:00
Evan Cheng
c4d1fb1435 Add a register class -> virtual registers map. 
llvm-svn: 57844
 2008-10-20 20:03:28 +00:00
Evan Cheng
9d9f1ff960 This forward declaration is unnecessary. 
llvm-svn: 57843
 2008-10-20 20:02:17 +00:00
Duncan Sands
9a3acf8d88 Support operations like fp_to_uint with a vector 
result type when the result type is legal but
not the operand type.  Add additional support
for EXTRACT_SUBVECTOR and CONCAT_VECTORS,
needed to handle such cases.

llvm-svn: 57840
 2008-10-20 16:31:21 +00:00
Duncan Sands
16503c7e76 Teach getTypeToTransformTo to return something 
sensible for vectors being scalarized.  Note
that this method can't return anything very
sensible when splitting non-power-of-two vectors.

llvm-svn: 57839
 2008-10-20 16:24:25 +00:00
Duncan Sands
53a9bbae16 LegalizeTypes support for atomic operation promotion. 
llvm-svn: 57838
 2008-10-20 16:17:42 +00:00
Duncan Sands
e2c4d654e3 Use DAG.getIntPtrConstant rather than DAG.getConstant 
with TLI.getPointerTy for a small simplification.

llvm-svn: 57837
 2008-10-20 16:14:43 +00:00
Duncan Sands
b912b4c4c4 Always use either MVT::i1 or getSetCCResultType for 
the condition of a SELECT node.  Make sure that the
correct extension type (any-, sign- or zero-extend)
is used.

llvm-svn: 57836
 2008-10-20 16:13:04 +00:00
Duncan Sands
81b834c160 Formatting - no functional change. 
llvm-svn: 57834
 2008-10-20 16:06:47 +00:00
Duncan Sands
1872cc22b0 Don't use a random type for the select condition, 
use an MVT::i1 and simplify the code while there.

llvm-svn: 57833
 2008-10-20 16:04:57 +00:00
Dan Gohman
1c36874fdd Fix a typo in a comment. 
llvm-svn: 57832
 2008-10-20 15:58:02 +00:00
Duncan Sands
98fc39f607 Have X86 custom lowering for LegalizeTypes use 
LowerOperation if it doesn't know what else to do.
This methods should probably be factorized some,
but this is good enough for the moment.  Have
LowerATOMIC_BINARY_64 use EXTRACT_ELEMENT rather
than assuming the operand is a BUILD_PAIR (if it
is then getNode will automagically simplify the
EXTRACT_ELEMENT).  This way LowerATOMIC_BINARY_64
usable from LegalizeTypes.

llvm-svn: 57831
 2008-10-20 15:56:33 +00:00
Matthijs Kooijman
3f50eb8347 Fix typo in a comment. 
llvm-svn: 57829
 2008-10-20 11:24:57 +00:00
Matthijs Kooijman
d63d1e317b Remove another stale comment. 
llvm-svn: 57828
 2008-10-20 11:23:18 +00:00
Matthijs Kooijman
ebb16d8ed5 Remove an inappropriate (probably outdated) comment. 
llvm-svn: 57827
 2008-10-20 11:21:12 +00:00
Matthijs Kooijman
360091f9fd Fix spelling error. 
llvm-svn: 57820
 2008-10-20 08:45:34 +00:00
Bill Wendling
ed477995f1 Set N->OperandList to 0 after deletion. Otherwise, it's possible that it will 
be either deleted or referenced afterwards.

llvm-svn: 57786
 2008-10-19 20:51:12 +00:00
Bill Wendling
980c8ad152 Fix comment. Other formatting changes. No functionality changes. 
llvm-svn: 57785
 2008-10-19 20:34:04 +00:00
Duncan Sands
0a9525febd Vector shuffle mask elements may be "undef". Handle 
this everywhere in LegalizeTypes.

llvm-svn: 57783
 2008-10-19 15:00:25 +00:00
Duncan Sands
65f39e9819 Use a legal integer type for vector shuffle mask 
elements.  Otherwise LegalizeTypes will, reasonably
enough, legalize the mask, which may result in it
no longer being a BUILD_VECTOR node (LegalizeDAG
simply ignores the legality or not of vector masks).

llvm-svn: 57782
 2008-10-19 14:58:05 +00:00
Chris Lattner
c369db13cc Reapply r57699 with a fix to not crash on asms with multiple results. Unlike 
the previous patch this one actually passes make check.

"Fix PR2356 on PowerPC: if we have an input and output that are tied together
that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand."

llvm-svn: 57771
 2008-10-18 18:49:30 +00:00
Dan Gohman
ea1d0d8823 Don't truncate GlobalAddress offsets to int in debug output. 
llvm-svn: 57770
 2008-10-18 18:22:42 +00:00
Evan Cheng
e742ce1a58 By min, I mean max. 
llvm-svn: 57766
 2008-10-18 05:21:37 +00:00
Evan Cheng
cf0977d7b1 When creating intervals, leave min(1, numdefs) holes after each instruction. 
llvm-svn: 57765
 2008-10-18 05:18:55 +00:00
Mon P Wang
772a4e2594 Make llvm memory barrier available as an intrinsic 
llvm-svn: 57750
 2008-10-18 02:48:13 +00:00
Dan Gohman
15597f07b2 Teach DAGCombine to fold constant offsets into GlobalAddress nodes, 
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.

llvm-svn: 57748
 2008-10-18 02:06:02 +00:00
Dan Gohman
2eaf4f1c48 Revert r57699. It's causing regressions in 
test/CodeGen/X86/2008-09-17-inline-asm-1.ll
and a few others, and it breaks the llvm-gcc build.

llvm-svn: 57747
 2008-10-18 01:03:45 +00:00
Dan Gohman
3386be03ea Use the opcode predicates, instead of duplicating the code. 
llvm-svn: 57735
 2008-10-17 21:42:45 +00:00
Dan Gohman
ac8c7772ba This is now partly done. 
llvm-svn: 57734
 2008-10-17 21:39:27 +00:00
Dan Gohman
69ac9cc00f This is done. 
llvm-svn: 57733
 2008-10-17 21:38:40 +00:00
Dan Gohman
e1e1c5197e Factor out the code for mapping LLVM IR condition opcodes to 
ISD condition opcodes into helper functions.

llvm-svn: 57726
 2008-10-17 21:16:08 +00:00
Evan Cheng
08d0796cf5 Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file. 
llvm-svn: 57723
 2008-10-17 21:02:22 +00:00
Evan Cheng
e7afdb2a42 Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers. 
TableGen has been taught to generate the lists from instruction definitions.

llvm-svn: 57722
 2008-10-17 21:00:09 +00:00
Evan Cheng
7792ca759d Fix PR2898. Spiller delete a store for reuse before it knows for sure the reuse happened. 
Patch by Lang Hames!

llvm-svn: 57720
 2008-10-17 20:56:41 +00:00
Chris Lattner
75618cbb6f add support for 128 bit aggregates. 
llvm-svn: 57715
 2008-10-17 19:59:51 +00:00
Bill Wendling
39b0625fe0 The Dwarf writer was comparing mangled and unmangled names for C++ code when we 
have an unreachable block in a function. This was triggering the assert. This is
a horrid hack to cover this up.

Oh! for a good debug info architecture!

llvm-svn: 57714
 2008-10-17 18:48:57 +00:00
Mon P Wang
fdfc9a2c4f Added MemIntrinsicNode which is useful to represent target intrinsics that 
touches memory and need an associated MemOperand

llvm-svn: 57712
 2008-10-17 18:22:58 +00:00
Dan Gohman
96269ec52a Factor out the code for mapping LLVM IR condition opcodes to 
ISD condition opcodes into helper functions.

llvm-svn: 57710
 2008-10-17 18:18:45 +00:00
Chris Lattner
d96b8d12bc add support for 128 bit inputs on both x86-64 and x86-32. 
llvm-svn: 57709
 2008-10-17 18:15:05 +00:00
Chris Lattner
231a9466df Fix a bug where the x86 backend would reject 64-bit r constraints when 
in 32-bit mode instead of assigning a register pair.  This has nothing to
do with PR2356, but I happened to notice it while working on it.

llvm-svn: 57704
 2008-10-17 17:59:52 +00:00
Chris Lattner
e2342cd790 Fix PR2356 on PowerPC: if we have an input and output that are tied together 
that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand.

llvm-svn: 57699
 2008-10-17 17:52:49 +00:00
Chris Lattner
d7b9ca9f8a remove an xfailed test. 
llvm-svn: 57695
 2008-10-17 17:26:48 +00:00
Chris Lattner
9876270b99 remove this test: it is xfailed anyway, and is failing for a reason 
other than why it was xfailed.

llvm-svn: 57694
 2008-10-17 17:26:19 +00:00
Evan Cheng
fa61b6a4ba Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0. 
llvm-svn: 57692
 2008-10-17 17:14:20 +00:00
Evan Cheng
733b305f24 getX86RegNum has long been moved to X86RegisterInfo. 
llvm-svn: 57691
 2008-10-17 17:12:18 +00:00
Chris Lattner
bb4ae53b94 refactor some code into a helper method, no functionality change. 
llvm-svn: 57690
 2008-10-17 17:05:25 +00:00
Chris Lattner
d748d12000 Keep track of *which* input constraint matches an output 
constraint.  Reject asms where an output has multiple
input constraints tied to it.

llvm-svn: 57687
 2008-10-17 16:47:46 +00:00
Chris Lattner
1d0742a530 add an assert so that PR2356 explodes instead of running off an 
array.  Improve some minor comments, refactor some helpers in
AsmOperandInfo.  No functionality change for valid code.

llvm-svn: 57686
 2008-10-17 16:21:11 +00:00
Gabor Greif
7a56f56cf4 remove spurious space in link 
llvm-svn: 57677
 2008-10-17 14:43:58 +00:00