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526 Commits

Author SHA1 Message Date
Bob Wilson
4ffb88d388 Check for comparisons of +/- zero when optimizing less-than-or-equal and 
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions.  This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.

llvm-svn: 97065
 2010-02-24 22:15:53 +00:00
Bob Wilson
84fc0200bd Use NEON vmin/vmax instructions for floating-point selects. 
Radar 7461718.

llvm-svn: 96572
 2010-02-18 06:05:53 +00:00
Bob Wilson
94eef3fc13 Fix pr6111: Avoid using the LR register for the target address of an indirect 
branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.

llvm-svn: 96360
 2010-02-16 17:24:15 +00:00
Dan Gohman
c40eb525ad Reapply the new LoopStrengthReduction code, with compile time and 
bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.

This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.

llvm-svn: 95975
 2010-02-12 10:34:29 +00:00
Bob Wilson
82d5534acc Delete dead PHI machine instructions. These can be created due to type 
legalization even when the IR-level optimizer has removed dead phis, such
as when the high half of an i64 value is unused on a 32-bit target.
I had to adjust a few test cases that had dead phis.
This is a partial fix for Radar 7627077.

llvm-svn: 95816
 2010-02-10 22:58:57 +00:00
Chris Lattner
20be5fb012 convert to filecheck. 
llvm-svn: 95608
 2010-02-08 23:47:34 +00:00
Evan Cheng
5541068ad3 Run codegen dce pass for all targets at all optimization levels. Previously it's 
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493
 2010-02-06 09:07:11 +00:00
Anton Korobeynikov
f7651ec593 Fix a gross typo: ARMv6+ may or may not support unaligned memory operations. 
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).

Allow unaligned memops on darwin and conservatively disallow them otherwise.

llvm-svn: 94889
 2010-01-30 14:08:12 +00:00
Chris Lattner
ee2b6b1cc5 emit jump table an alias ".set" directives through MCStreamer as 
assignments.

.set x, a-b

is the same as:

x = a-b

llvm-svn: 94596
 2010-01-26 21:53:08 +00:00
Rafael Espindola
f46baf3304 Emit .comm alignment in bytes but .align in powers of 2 for ARM ELF. 
Original patch by Sandeep Patel and updated by me.

llvm-svn: 94582
 2010-01-26 20:21:43 +00:00
Rafael Espindola
575697fd65 Update test for darwin. 
llvm-svn: 94421
 2010-01-25 15:32:10 +00:00
Rafael Espindola
82a8b3efd4 Fix PR6134. 
We are not emitting alignments on Darwin for "bar". Not sure what is the
correct way to do it.

llvm-svn: 94400
 2010-01-25 02:27:39 +00:00
Dan Gohman
525f7d7833 Revert LoopStrengthReduce.cpp to pre-r94061 for now. 
llvm-svn: 94123
 2010-01-22 00:46:49 +00:00
Dan Gohman
be34c35f32 Re-implement the main strength-reduction portion of LoopStrengthReduction. 
This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.

It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.

llvm-svn: 94061
 2010-01-21 02:09:26 +00:00
Evan Cheng
572390be3b Test case for r93758. 
llvm-svn: 93824
 2010-01-19 00:35:20 +00:00
Bob Wilson
72cf548263 The Neon "vtst" instruction takes a suffix that is the element size alone -- 
adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax.  This helps us pass a few more
of the Neon tests from gcc.

llvm-svn: 93677
 2010-01-17 06:35:17 +00:00
Bob Wilson
3386047bdb Run the pre-register allocation tail duplication pass by default. Remove 
the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.

llvm-svn: 93597
 2010-01-16 00:29:50 +00:00
Chris Lattner
1b6c061cd0 remove uses of deprecated functions, this generates slightly 
different BlockAddress labels, but nothing semantically important.

Add a FIXME that BlockAddress codegen is broken if the LLVM BB has 
an empty name (e.g. strip was run).

llvm-svn: 93303
 2010-01-13 07:30:49 +00:00
Dan Gohman
5fa04f2707 Delete useless trailing semicolons. 
llvm-svn: 92740
 2010-01-05 17:55:26 +00:00
Chris Lattner
3d38dbff2a Make this more likely to generate a libcall. 
llvm-svn: 92387
 2010-01-01 03:26:51 +00:00
Bob Wilson
a9f20f9f6e Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.

llvm-svn: 91649
 2009-12-18 01:03:29 +00:00
Evan Cheng
edcc21919f - Support inline asm 'w' constraint for 128-bit vector types. 
- Also support the 'q' NEON registers asm code.

llvm-svn: 90894
 2009-12-08 23:06:22 +00:00
Bob Wilson
b53c801366 Recognize canonical forms of vector shuffles where the same vector is used for 
both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.

llvm-svn: 90417
 2009-12-03 06:40:55 +00:00
Evan Cheng
fcbc30f36e Fix PR5614: parts of a physical register def may be killed the rest. 
llvm-svn: 90180
 2009-12-01 00:44:45 +00:00
Anton Korobeynikov
0f885eb7fd Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
 2009-11-24 00:44:37 +00:00
Jim Grosbach
76b545e988 move fconst[sd] to UAL. <rdar://7414913> 
llvm-svn: 89700
 2009-11-23 21:08:25 +00:00
Edward O'Callaghan
d1c7b40bb5 Convert ARM tests to FileCheck for PR5307. 
llvm-svn: 89593
 2009-11-22 14:23:33 +00:00
Edward O'Callaghan
1a250b4109 Forgot to alter RUN line when converting to FileCheck. 
llvm-svn: 89588
 2009-11-22 13:09:48 +00:00
Edward O'Callaghan
5ae4559914 Fix for bad FileCheck converts in revision 89584. 
llvm-svn: 89586
 2009-11-22 12:50:05 +00:00
Edward O'Callaghan
949850890f Convert a few tests to FileCheck for PR5307. 
llvm-svn: 89584
 2009-11-22 11:45:44 +00:00
Jim Grosbach
99c5b49c61 Revert 89562. We're being sneakier than I was giving us credit for, and this 
isn't necessary.

llvm-svn: 89568
 2009-11-21 23:34:09 +00:00
Jim Grosbach
d4603a5c4e Darwin requires a frame pointer for all non-leaf functions to support correct 
backtraces.

llvm-svn: 89562
 2009-11-21 21:40:08 +00:00
Evan Cheng
9f57c4916e Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Evan Cheng
405012b096 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. 
llvm-svn: 89423
 2009-11-20 00:54:03 +00:00
Bob Wilson
70bfa110eb Fix buildbots. 
llvm-svn: 89274
 2009-11-18 23:30:38 +00:00
Bob Wilson
dccd3bdb4e Tail duplication still needs to iterate. Duplicating new instructions onto 
the tail of a block may make that block a new candidate for duplication.

llvm-svn: 89264
 2009-11-18 22:52:37 +00:00
Anton Korobeynikov
6b1a243be8 Forgot to commit test fixes 
llvm-svn: 89138
 2009-11-17 20:38:36 +00:00
Jim Grosbach
1aa571da3c Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

llvm-svn: 88874
 2009-11-15 21:45:34 +00:00
Evan Cheng
9b46e74f42 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745
 2009-11-14 02:55:43 +00:00
Evan Cheng
3781b2e7b3 Add radar number. 
llvm-svn: 88739
 2009-11-14 02:11:32 +00:00
Evan Cheng
c56b0a0f14 Fix PR5412: Fix an inverted check and another missing sub-register check. 
llvm-svn: 88738
 2009-11-14 02:09:09 +00:00
Evan Cheng
e2907b91de Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers. 
llvm-svn: 88719
 2009-11-13 23:16:41 +00:00
Evan Cheng
f629fdcab2 Fix PR5410: LiveVariables lost subreg def: 
D0<def,dead> = ...
...
             = S0<use, kill>
S0<def>      = ...
...
D0<def>      = 

The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.

llvm-svn: 88690
 2009-11-13 20:36:40 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Anton Korobeynikov
30095499fc It turns out that the testcase in question uncovered subreg-handling bug. 
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

llvm-svn: 86375
 2009-11-07 15:20:32 +00:00
Anton Korobeynikov
dca40933ee Honour subreg machine operands during asmprinting 
llvm-svn: 86303
 2009-11-06 23:45:15 +00:00
Bob Wilson
e79354a831 Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301
 2009-11-06 23:33:28 +00:00
Evan Cheng
aaf30ce699 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
llvm-svn: 86294
 2009-11-06 22:24:13 +00:00
Dan Gohman
229f9edf7a Update these tests for the new label names. 
llvm-svn: 86192
 2009-11-05 23:31:40 +00:00
Bob Wilson
d14be3d83c Attempt again to fix buildbot failures: make expected output less specific 
and compile with -mtriple to specify *-apple-darwin targets.

llvm-svn: 86081
 2009-11-05 00:30:35 +00:00
Bob Wilson
9e30ecad4e Fix broken test. 
llvm-svn: 86045
 2009-11-04 20:04:11 +00:00
Bob Wilson
ca42ca296d Add test for ARM indirectbr codegen. 
llvm-svn: 86042
 2009-11-04 19:25:34 +00:00
Evan Cheng
caab17007b fconsts / fconstd immediate should be proceeded with #. 
llvm-svn: 85952
 2009-11-03 21:59:33 +00:00
Evan Cheng
d783406059 Re-apply 85799. It turns out my code isn't buggy. 
llvm-svn: 85947
 2009-11-03 21:40:02 +00:00
Evan Cheng
ed22395c61 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
llvm-svn: 85871
 2009-11-03 05:52:54 +00:00
Anton Korobeynikov
48b30c79be Revert r85049, it is causing PR5367 
llvm-svn: 85847
 2009-11-03 00:24:48 +00:00
Evan Cheng
ca5847665b Revert 85799 for now. It might be breaking llvm-gcc driver. 
llvm-svn: 85827
 2009-11-02 21:49:14 +00:00
Evan Cheng
ec5cb0cdbd Initilize the machine LICM CSE map upon the first time an instruction is hoisted to 
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.

llvm-svn: 85799
 2009-11-02 08:09:49 +00:00
Evan Cheng
ce9d8e2737 Remove an irrelevant and poorly reduced test case. 
llvm-svn: 85794
 2009-11-02 07:11:54 +00:00
Anton Korobeynikov
09147da530 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
llvm-svn: 85767
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
ed410a8ee3 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
llvm-svn: 85765
 2009-11-02 00:11:06 +00:00
Jim Grosbach
5b094f3b36 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

llvm-svn: 85697
 2009-10-31 22:57:36 +00:00
Jim Grosbach
2a445e5d0a Update test to be more explicit about what instruction sequences are expected for each operation. 
llvm-svn: 85689
 2009-10-31 21:52:58 +00:00
Jim Grosbach
ace75c4288 Expand 64-bit logical shift right inline 
llvm-svn: 85687
 2009-10-31 21:42:19 +00:00
Jim Grosbach
16ae289667 Expand 64-bit arithmetic shift right inline 
llvm-svn: 85685
 2009-10-31 21:00:56 +00:00
Jim Grosbach
534d2cb249 Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675
 2009-10-31 19:38:01 +00:00
Benjamin Kramer
60dac7de40 Add missing colons for FileCheck. 
llvm-svn: 85674
 2009-10-31 19:22:24 +00:00
Jim Grosbach
78a5bcfa02 Convert to FileCheck 
llvm-svn: 85673
 2009-10-31 19:06:53 +00:00
Rafael Espindola
d4fadd76da This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590
 2009-10-30 14:33:14 +00:00
Evan Cheng
1babe43881 Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Rafael Espindola
9cafe9e468 Add missing testcase. 
llvm-svn: 85266
 2009-10-27 17:59:03 +00:00
Bob Wilson
cc098c98de Fix the rest of the ARM failures by converting them to FileCheck. 
llvm-svn: 85208
 2009-10-27 06:16:45 +00:00
Bob Wilson
5753a34ebb Fix some more failures by converting to FileCheck. 
llvm-svn: 85207
 2009-10-27 05:50:28 +00:00
Bob Wilson
37191c825b Convert to FileCheck, fixing failure due to tab change in the process. 
llvm-svn: 85204
 2009-10-27 05:30:47 +00:00
Evan Cheng
1c169777ca Update tests. 
llvm-svn: 85050
 2009-10-25 07:53:48 +00:00
Bob Wilson
8f4f73da55 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
llvm-svn: 84868
 2009-10-22 16:52:21 +00:00
Evan Cheng
2edd1efa46 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
llvm-svn: 84843
 2009-10-22 06:48:32 +00:00
Evan Cheng
8fdd1661fa Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
llvm-svn: 84813
 2009-10-22 00:40:00 +00:00
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Anton Korobeynikov
7b6fe9f251 Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign) 
transform.

llvm-svn: 84683
 2009-10-20 21:37:45 +00:00
Chris Lattner
b9bbaf7f4d convert to filecheck syntax and make a lot more aggressive. 
llvm-svn: 84517
 2009-10-19 18:27:56 +00:00
Chris Lattner
6fd5bc3ba0 rename test 
llvm-svn: 84515
 2009-10-19 18:18:07 +00:00
Evan Cheng
b1580b5c48 Enable post-alloc scheduling for all ARM variants except for Thumb1. 
llvm-svn: 84249
 2009-10-16 06:11:08 +00:00
Bob Wilson
d66a3fd73b Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
 2009-10-13 20:50:28 +00:00
Sandeep Patel
1584038783 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
llvm-svn: 84009
 2009-10-13 18:59:48 +00:00
Benjamin Kramer
34c117d8b7 Eliminate some redundant llvm-as calls. 
llvm-svn: 83837
 2009-10-12 09:31:55 +00:00
Dan Gohman
b535009219 Update this test; the code is the same but it gets counted as one 
fewer remat.

llvm-svn: 83690
 2009-10-09 23:31:04 +00:00
Bob Wilson
011e458c11 Merge a bunch of NEON tests into larger files so they run faster. 
llvm-svn: 83667
 2009-10-09 20:20:54 +00:00
Bob Wilson
de71518edb Convert some ARM tests with lots of greps to use FileCheck. 
llvm-svn: 83651
 2009-10-09 17:20:46 +00:00
Bob Wilson
d48cacb92f Commit one last NEON test to use FileCheck. That's all of them now! 
llvm-svn: 83617
 2009-10-09 05:31:56 +00:00
Bob Wilson
a8746e6bd1 Convert more NEON tests to use FileCheck. 
llvm-svn: 83616
 2009-10-09 05:14:48 +00:00
Bob Wilson
8092fef09a Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
llvm-svn: 83600
 2009-10-09 00:01:36 +00:00
Bob Wilson
979cb24a81 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
llvm-svn: 83598
 2009-10-08 23:51:31 +00:00
Bob Wilson
233992bc56 Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson
395adfabef Convert more NEON tests to use FileCheck. 
llvm-svn: 83595
 2009-10-08 23:33:03 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson
1fe8b7e27c Convert more NEON tests to use FileCheck. 
llvm-svn: 83587
 2009-10-08 22:33:53 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Anton Korobeynikov
f9c811c948 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. 
llvm-svn: 83572
 2009-10-08 20:43:22 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00