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5015 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
1ffbef8ad1 Add a DAGCombine for subvector extracts to remove useless chains of 
subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.

llvm-svn: 140204
 2011-09-20 23:19:33 +00:00
Bruno Cardoso Lopes
629e7c2410 Revert r140097, working on a better approach 
llvm-svn: 140203
 2011-09-20 23:19:29 +00:00
Evan Cheng
ead45e2ba6 Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911. 
llvm-svn: 140181
 2011-09-20 21:38:18 +00:00
NAKAMURA Takumi
595c0c8e15 test/CodeGen/X86/avx-minmax.ll: Unbreak Win32. 
On Windows x64, 128-bit arguments are not passed by reg but by indirect. eg.

maxpd:
        vmovapd (%rcx), %xmm0
        vmaxpd  (%rdx), %xmm0, %xmm0

FIXME: I don't care YMM on x64 for now.
llvm-svn: 140143
 2011-09-20 14:11:35 +00:00
Craig Topper
df17f1cc99 Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd. 
llvm-svn: 140140
 2011-09-20 07:38:59 +00:00
Andrew Trick
53aeb9f663 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134
 2011-09-20 03:17:40 +00:00
Bruno Cardoso Lopes
bed7ef51b6 Attempt to fix -mtriple=i686-{cygwin|mingw|win32} regressions. Nakamura, 
if this doesn't work, please provide more details.

llvm-svn: 140107
 2011-09-20 00:08:12 +00:00
Bruno Cardoso Lopes
7cf7f02c3d Based on the small opt Zvi's patch was trying to achieve, eliminate 
128-bit undef subvector insertion into a 256-bit vector

llvm-svn: 140097
 2011-09-19 23:36:50 +00:00
Eli Friedman
b11676fb4b Some additional tests for Thumb atomic load and store (which I somehow forgot to commit earlier). 
llvm-svn: 140074
 2011-09-19 22:02:33 +00:00
Bruno Cardoso Lopes
9e5ef44daf Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix 
PR10955 and PR10948.

llvm-svn: 140069
 2011-09-19 21:29:24 +00:00
Nadav Rotem
1cfdc59e94 setOperationAction should be done on the return value of the type, not the operands. 
llvm-svn: 140001
 2011-09-18 14:57:03 +00:00
Nadav Rotem
cfc77bc719 When promoting integer vectors we often create ext-loads. This patch adds a 
dag-combine optimization to implement the ext-load efficiently (using shuffles).

For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.

llvm-svn: 139995
 2011-09-18 10:39:32 +00:00
Benjamin Kramer
547157073b Apply Duncan's test fix from r139986 to the avx version of that test too. 
llvm-svn: 139992
 2011-09-18 00:41:38 +00:00
Duncan Sands
4149334f09 Synthesize x86 max/min instructions also for vectors (i.e. produce 
maxps and maxpd).  This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it.  Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.

llvm-svn: 139986
 2011-09-17 16:49:39 +00:00
Andrew Trick
10ea51b841 Test case trial and error. Not sure the proper way to check MBB names. 
llvm-svn: 139900
 2011-09-16 03:57:19 +00:00
Andrew Trick
5be06c8057 Reduced a stronger test case for coalescer bug PR10920. 
llvm-svn: 139898
 2011-09-16 03:46:49 +00:00
Eli Friedman
f7bb39b592 Some legalization fixes for atomic load and store. 
llvm-svn: 139851
 2011-09-15 21:20:49 +00:00
Jakob Stoklund Olesen
b36a98d18f VirtRegMap is counting spill slots, not register spills. 
Fix the stats counters to reflect that.

llvm-svn: 139819
 2011-09-15 18:31:13 +00:00
Bruno Cardoso Lopes
8e702bba63 Change all checks regarding the presence of any SSE level to always 
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite

llvm-svn: 139817
 2011-09-15 18:27:36 +00:00
Andrew Trick
e5bb7267ff [regcoalescing] bug fix for RegistersDefinedFromSameValue. 
An improper SlotIndex->VNInfo lookup was leading to unsafe copy removal.
Fixes PR10920 401.bzip2 miscompile with no IV rewrite.

llvm-svn: 139765
 2011-09-15 01:09:33 +00:00
Nadav Rotem
8e3edccebe Add integer promotion support for vselect 
llvm-svn: 139692
 2011-09-14 14:42:15 +00:00
Bruno Cardoso Lopes
3e6b9661d1 Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss". 
llvm-svn: 139686
 2011-09-14 02:36:14 +00:00
Devang Patel
75c70b2315 Remove ancient debug info constructs from test cases, they are not relevant to test case's main objective. 
llvm-svn: 139675
 2011-09-14 00:29:50 +00:00
Devang Patel
f9dcd6261d Remove unnecessary old test. 
llvm-svn: 139674
 2011-09-14 00:28:54 +00:00
Akira Hatanaka
3d26b79a9a Delete test cases that generate code for allegrex/psp and cannot be repurposed. 
llvm-svn: 139652
 2011-09-13 22:29:13 +00:00
Eli Friedman
f13b5ef0e1 Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case. 
llvm-svn: 139641
 2011-09-13 20:50:54 +00:00
Akira Hatanaka
44c745931f Add pattern used to match MipsLo, which is needed when the instruction selector 
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead

llvm-svn: 139634
 2011-09-13 20:13:58 +00:00
Akira Hatanaka
1376e1eabf Disable tests which generate code for allegrex or psp. 
llvm-svn: 139632
 2011-09-13 20:00:35 +00:00
Nadav Rotem
5ea703debf update checked pattern 
llvm-svn: 139631
 2011-09-13 19:59:18 +00:00
Nadav Rotem
60df99b809 Add vselect target support for targets that do not support blend but do support 
xor/and/or (For example SSE2).

llvm-svn: 139623
 2011-09-13 19:17:42 +00:00
Andrew Trick
a534a558a2 Generalize this test's CHECK statements to handle different indvars modes. 
llvm-svn: 139577
 2011-09-13 02:46:27 +00:00
Bruno Cardoso Lopes
eb09ab7c3f Change testcase commandline to be more strict and silence buildbots 
llvm-svn: 139554
 2011-09-12 22:59:26 +00:00
Bruno Cardoso Lopes
a4d2bdfa40 Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and 
destination types are equal!

llvm-svn: 139553
 2011-09-12 22:59:23 +00:00
Bruno Cardoso Lopes
64e2e852f9 Revert the wrong part of r139528, and fix testcases. 
llvm-svn: 139541
 2011-09-12 21:24:07 +00:00
Bruno Cardoso Lopes
c67e996fc3 Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't. 
However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

llvm-svn: 139528
 2011-09-12 19:30:40 +00:00
Eli Friedman
08926ecbfb Fix mistake in test runline. 
llvm-svn: 139505
 2011-09-12 17:32:58 +00:00
Richard Osborne
962b1ca071 Associate a MemOperand with LDWCP nodes introduced during ISel. 
This information is required if we want LDWCP to be hoisted out of loops.

llvm-svn: 139495
 2011-09-12 14:43:23 +00:00
Eli Friedman
2275f7612e Really un-XFAIL the testcase, like I said I would in r139458. 
llvm-svn: 139459
 2011-09-10 02:02:27 +00:00
Richard Trieu
0485e133f2 Fixed an assert from: 
assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454
 2011-09-10 01:26:21 +00:00
Akira Hatanaka
a8f0f7babb Fix test cases. 
Generate code for Mips32r1 unless a Mips32r2 feature is tested.

llvm-svn: 139433
 2011-09-09 23:14:58 +00:00
Eli Friedman
4bae1c4f70 Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. 
llvm-svn: 139407
 2011-09-09 21:04:06 +00:00
Akira Hatanaka
f65d050693 Drop support for Mips1 and Mips2. 
llvm-svn: 139405
 2011-09-09 20:45:50 +00:00
Nadav Rotem
ccb46031e6 Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type 
llvm-svn: 139400
 2011-09-09 20:29:17 +00:00
Akira Hatanaka
17df2dfe8c Drop support for Allegrex. Allegrex implements a variant of Mips2. 
llvm-svn: 139383
 2011-09-09 19:00:51 +00:00
Akira Hatanaka
e1eb015eb9 Change default target architecture from Mips1 to Mips32r1 in preparation for 
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344
 2011-09-09 01:13:27 +00:00
Devang Patel
ba2d56b1ef Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. 
llvm-svn: 139330
 2011-09-08 22:59:09 +00:00
Bruno Cardoso Lopes
54962ac233 Add a AVX version of a simple i64 -> f64 bitcast. This could be 
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320
 2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
50596b096c Reapply testcase from r139309! 
llvm-svn: 139318
 2011-09-08 21:05:43 +00:00
Bruno Cardoso Lopes
3ecc7a69fd Remove this crashing test, until I figure out what's going wrong here 
llvm-svn: 139309
 2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes
74a67e22b0 Add AVX versions of blend vector operations and fix some issues noticed 
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305
 2011-09-08 18:05:08 +00:00