Jim Grosbach
3f5493c136
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0 " should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
Jim Grosbach
54372eef76
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
...
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
Jim Grosbach
bd33fc6efd
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
Jim Grosbach
0ba5ba4535
ARM pre-UAL NEG mnemonic for convenience when porting old code.
...
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
Jim Grosbach
356ad6d232
ARM assembly aliases for BIC<-->AND (immediate).
...
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
Jim Grosbach
c1cf417595
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
Jim Grosbach
5b4f7d74de
ARM mode 'mul' operand ordering tweak.
...
Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
Jim Grosbach
fe5f0cfa29
Generalize the fixup info for ARM mode.
...
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
2011-11-16 22:48:37 +00:00
Jim Grosbach
b8ebc386df
ARM assembly parsing two operand forms for shift instructions.
...
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
Jim Grosbach
8b1d4c989c
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
llvm-svn: 144688
2011-11-15 20:02:06 +00:00
Jim Grosbach
f5943e4c5e
ARM assembly parsing for LSR/LSL/ROR(immediate).
...
More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999
ARM assembly parsing for ASR(immediate).
...
Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
Owen Anderson
2021ad2133
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
...
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
Owen Anderson
ffca195c01
Fix tests for corrected MSR encodings.
...
llvm-svn: 142622
2011-10-20 21:53:19 +00:00
Jim Grosbach
2a501996ab
ARM encoding tests for STC.
...
llvm-svn: 141787
2011-10-12 17:36:13 +00:00
Jim Grosbach
eb7acc978a
ARM parsing and encoding for the <option> form of LDC/STC instructions.
...
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
Jim Grosbach
d2cfc2b31f
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
Jim Grosbach
d9a8af05ea
Tidy up.
...
llvm-svn: 140114
2011-09-20 00:24:37 +00:00
Jim Grosbach
d4a347b1e8
Tidy up a bit.
...
llvm-svn: 140096
2011-09-19 23:34:18 +00:00
Jim Grosbach
6e092f297b
Remove FIXME. TBB/TBH are Thumb mode only instructions.
...
llvm-svn: 140048
2011-09-19 20:30:29 +00:00
Jim Grosbach
4c944a22e2
Fix comment.
...
llvm-svn: 139919
2011-09-16 18:03:00 +00:00
Jim Grosbach
aeb7320fa5
Add some missing 'CHECK' lines and tidy up others.
...
llvm-svn: 139849
2011-09-15 21:17:38 +00:00
Jim Grosbach
b1c70aab3e
Thumb2 assembly parsing and encoding for MSR/MRS.
...
Fix a bug in handling default flags for both ARM and Thumb encodings.
llvm-svn: 139721
2011-09-14 20:03:46 +00:00
Jim Grosbach
f310295150
Tidy up formatting a bit.
...
llvm-svn: 139396
2011-09-09 20:17:49 +00:00
Jim Grosbach
36ea6726dd
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
Owen Anderson
e14d6edccc
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
...
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
Owen Anderson
8719e2c1c3
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
...
llvm-svn: 138739
2011-08-29 17:17:09 +00:00
Owen Anderson
fd21da3506
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
Owen Anderson
9b85a034c9
Correct encoding of BL with immediate offset.
...
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
Owen Anderson
86b11d01eb
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
Owen Anderson
4854258d9c
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
Jim Grosbach
41ef68eb17
Fix tests per now-correct encoding as of r137371.
...
llvm-svn: 137376
2011-08-11 22:31:48 +00:00
Jim Grosbach
e6bd3a1ab8
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
Jim Grosbach
9717a9c0d3
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Jim Grosbach
abaaf4513f
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Jim Grosbach
9f0533c5d2
ARM SRS instruction parsing, diassembly and encoding support.
...
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Jim Grosbach
1b69dbc796
ARM assembly parsing and encoding for RFE instruction.
...
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Jim Grosbach
43e281bec4
ARM update tests for CPS instruction.
...
llvm-svn: 136472
2011-07-29 17:39:27 +00:00
Jim Grosbach
666e97a0ce
CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
...
llvm-svn: 136408
2011-07-28 21:59:38 +00:00
Jim Grosbach
01d878a4ea
ARM assembly parsing and encoding for BLX (immediate).
...
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.
llvm-svn: 136406
2011-07-28 21:57:55 +00:00
Jim Grosbach
adeee03ea2
Remove obsolete FIXME reference in comment.
...
llvm-svn: 136400
2011-07-28 21:37:05 +00:00
Jim Grosbach
3bbf68ce6e
ARM assembly parsing and encoding for BFC and BFI.
...
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).
llvm-svn: 136399
2011-07-28 21:34:26 +00:00
Jim Grosbach
2378f8a15e
ARM parsing and encoding for ADR.
...
The label does not have a '#' prefix. Add parsing and encoding tests.
llvm-svn: 136360
2011-07-28 16:33:54 +00:00
Jim Grosbach
68241cddd8
Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
...
llvm-svn: 136358
2011-07-28 16:00:41 +00:00
Jim Grosbach
992112a797
ARM parsing and encoding tests.
...
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.
llvm-svn: 136312
2011-07-28 00:37:03 +00:00
Jim Grosbach
37586957ee
ARM assembly parsing and encoding for USUB16 and USUB8.
...
llvm-svn: 136289
2011-07-27 23:10:05 +00:00
Jim Grosbach
3e48c1f676
ARM assembly parsing and encoding for USAX.
...
llvm-svn: 136288
2011-07-27 23:07:00 +00:00
Jim Grosbach
b0bde240c1
Clean up tabs.
...
llvm-svn: 136286
2011-07-27 22:35:06 +00:00
Jim Grosbach
094803b4d0
ARM assembly parsing and encoding support for USAT and USAT16.
...
Use range checked immediate operands for instructions. Add tests.
llvm-svn: 136285
2011-07-27 22:34:17 +00:00