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Commit Graph

1650 Commits

Author SHA1 Message Date
Bob Wilson
233992bc56 Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
llvm-svn: 83596
2009-10-08 23:38:24 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
2009-10-08 22:53:57 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
llvm-svn: 83585
2009-10-08 22:27:33 +00:00
Anton Korobeynikov
f9c811c948 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
llvm-svn: 83572
2009-10-08 20:43:22 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
llvm-svn: 83568
2009-10-08 18:56:10 +00:00
Bob Wilson
0159d0d864 Clean up some unnecessary initializations.
llvm-svn: 83566
2009-10-08 18:52:56 +00:00
Bob Wilson
c62c9946e2 Clean up a comment (indentation was wrong).
llvm-svn: 83565
2009-10-08 18:51:31 +00:00
Bob Wilson
276bdabb9a Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
llvm-svn: 83526
2009-10-08 05:18:18 +00:00
Jim Grosbach
9f57f9bee6 Cleanup up unused R3LiveIn tracking.
llvm-svn: 83522
2009-10-08 01:50:26 +00:00
Jim Grosbach
a3e1149941 Re-enable register scavenging in Thumb1 by default.
llvm-svn: 83521
2009-10-08 01:46:59 +00:00
Bob Wilson
8aa1d328b5 Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
llvm-svn: 83518
2009-10-08 00:28:28 +00:00
Bob Wilson
958e4ae815 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
llvm-svn: 83513
2009-10-08 00:21:01 +00:00
Bob Wilson
729cd181a2 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
llvm-svn: 83508
2009-10-07 23:54:04 +00:00
Bob Wilson
3cbf156518 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
llvm-svn: 83506
2009-10-07 23:39:57 +00:00
Bob Wilson
0ffa9679a5 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
llvm-svn: 83502
2009-10-07 22:57:01 +00:00
Jim Grosbach
cb905d28a8 reverting thumb1 scavenging default due to test failure while I figure out what's up.
llvm-svn: 83501
2009-10-07 22:49:41 +00:00
Jim Grosbach
a9d83ba92c Enable thumb1 register scavenging by default.
llvm-svn: 83494
2009-10-07 22:26:14 +00:00
Bob Wilson
e7173601a3 Add some instruction encoding bits for NEON load/store instructions.
llvm-svn: 83490
2009-10-07 21:53:04 +00:00
Bob Wilson
cee91108da Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
llvm-svn: 83486
2009-10-07 20:49:18 +00:00
Bob Wilson
af14187764 Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
llvm-svn: 83484
2009-10-07 20:30:08 +00:00
Bob Wilson
62a3e55cea Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
llvm-svn: 83482
2009-10-07 18:47:39 +00:00
Bob Wilson
9bb47b3e5d Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
llvm-svn: 83479
2009-10-07 18:09:32 +00:00
Kevin Enderby
c0d0a1ec58 Add another bit of the ARM target assembler to llvm-mc to parse registers
with writeback, things like "sp!", etc.  Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.

llvm-svn: 83477
2009-10-07 18:01:35 +00:00
Bob Wilson
b38401ccef Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
llvm-svn: 83471
2009-10-07 17:24:55 +00:00
Bob Wilson
a77f6a7814 Rearrange code for selecting vld2 intrinsics. No functionality change.
This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470
2009-10-07 17:23:09 +00:00
Jim Grosbach
61c5ce1bde Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.

llvm-svn: 83467
2009-10-07 17:12:56 +00:00
Anton Korobeynikov
aba66ae89b Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
and register spills.

llvm-svn: 83435
2009-10-07 00:06:35 +00:00
Kevin Enderby
2c772c1ae9 Added bits of the ARM target assembler to llvm-mc to parse some load instruction
operands.  Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts.  This is a work in progress.

llvm-svn: 83424
2009-10-06 22:26:42 +00:00
Bob Wilson
8cd1ea81c4 Add codegen support for NEON vld2 operations on quad registers.
llvm-svn: 83422
2009-10-06 22:01:59 +00:00
Bob Wilson
8c108dc476 Use copyRegToReg hook to copy registers.
llvm-svn: 83421
2009-10-06 22:01:15 +00:00
Bob Wilson
21056e1c2e Fix a comment typo.
Patch by Johnny Chen.

llvm-svn: 83407
2009-10-06 20:18:46 +00:00
Dan Gohman
a803c712dd Instead of printing unnecessary basic block labels as labels in
verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.

Also, factor out the relevant code out of all the targets and into
target-independent code.

llvm-svn: 83392
2009-10-06 17:38:38 +00:00
Devang Patel
a8f35ac640 Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction.
llvm-svn: 83363
2009-10-06 02:19:11 +00:00
Jim Grosbach
d6da133b85 In Thumb1, the register scavenger is not always able to use an emergency
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.

llvm-svn: 83336
2009-10-05 22:30:23 +00:00
Chris Lattner
a3cf123e86 strength reduce a ton of type equality tests to check the typeid (Through
the new predicates I added) instead of going through a context and doing a
pointer comparison.  Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.

llvm-svn: 83297
2009-10-05 05:54:46 +00:00
Bob Wilson
64ce6ef65a Add a comment to describe letters used in multiclass name suffixes.
llvm-svn: 83257
2009-10-03 04:44:16 +00:00
Bob Wilson
be258e083a Fix encoding problem for VMLS instruction.
Thanks to Johnny Chen for pointing this out!

llvm-svn: 83256
2009-10-03 04:41:21 +00:00
Evan Cheng
8cf9f56cca getFunctionAlignment should return log2 alignment.
llvm-svn: 83242
2009-10-02 06:57:25 +00:00
Evan Cheng
5b9107c1b9 Forgot about ARM::tPUSH. It also has a new writeback operand.
llvm-svn: 83237
2009-10-02 05:03:07 +00:00
Evan Cheng
d6e64a4cfd Move load / store multiple before post-alloc scheduling.
llvm-svn: 83236
2009-10-02 04:57:15 +00:00
David Goodwin
a4b73e486e Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
llvm-svn: 83218
2009-10-01 22:19:57 +00:00
David Goodwin
d0edce4c0d Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
llvm-svn: 83215
2009-10-01 21:46:35 +00:00
Evan Cheng
272a738580 ARM::tPOP and tPOP_RET each has an extra writeback operand now.
llvm-svn: 83214
2009-10-01 20:54:53 +00:00
Evan Cheng
241092d89f Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.

llvm-svn: 83197
2009-10-01 08:22:27 +00:00
Evan Cheng
dc5ac208bf Update ARM JIT emitter to account for ld/st multiple changes.
llvm-svn: 83192
2009-10-01 01:39:21 +00:00
Evan Cheng
4dd7d7156e Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
Devang Patel
e097bf49d0 Use MachineInstr as an processDebugLoc() argument.
This will allow processDebugLoc() to handle scopes for DWARF debug info. 

llvm-svn: 83183
2009-09-30 23:12:50 +00:00
Bob Wilson
d6896006b1 Use OutStreamer.SwitchSection instead of writing out textual section directives.
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.

llvm-svn: 83178
2009-09-30 22:25:37 +00:00
Bob Wilson
1cf44c8225 Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this
to emit target-specific things at the beginning of the asm output.  This
fixes a problem for PPC, where the text sections are not being kept together
as expected.  The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives.  The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text.  With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.

llvm-svn: 83176
2009-09-30 22:06:26 +00:00
Bob Wilson
233aa46c87 The AsmPrinter base class contains a DwarfWriter member, so there's no need
for derived AsmPrinters to add another one.  In some cases, fixing this
removes the need to override the doInitialization method.

llvm-svn: 83170
2009-09-30 21:24:45 +00:00