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1650 Commits

Author SHA1 Message Date
Anton Korobeynikov
fa4c7562d5 Define proper subreg sets for arm - this should fix bunch of subtle problems 
with subreg - superreg mapping and also fix PR4965.

llvm-svn: 81657
 2009-09-13 00:59:43 +00:00
Anton Korobeynikov
267bd0c577 Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to 
constraint the register usage.

llvm-svn: 81635
 2009-09-12 22:21:08 +00:00
Jim Grosbach
932453f233 Revert array initialization regclass change so that the initialization stays static, not runtime. 
llvm-svn: 81560
 2009-09-11 20:13:17 +00:00
Jim Grosbach
6293edbcbf Update register class references to use the global constant ARM::*RegisterClass names. 
llvm-svn: 81556
 2009-09-11 19:49:06 +00:00
Evan Cheng
0e0590db1b Proper support of non-lazy indirect symbols. 
llvm-svn: 81422
 2009-09-10 01:23:53 +00:00
Evan Cheng
7f25e554e4 Fix double load / store multiple encoding. 
llvm-svn: 81403
 2009-09-09 23:55:03 +00:00
Bob Wilson
877a857b4b Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS. 
See the bug report for details.

llvm-svn: 81397
 2009-09-09 23:14:54 +00:00
Chris Lattner
b9aca1a178 remove DebugLoc from MCInst and eliminate "Comment printing" from 
the MCInst path of the asmprinter.  Instead, pull comment printing
out of the autogenerated asmprinter into each target that uses the
autogenerated asmprinter.  This causes code duplication into each
target, but in a way that will be easier to clean up later when more
asmprinter stuff is commonized into the base AsmPrinter class.

This also fixes an xcore strangeness where it inserted two tabs
before every instruction.

llvm-svn: 81396
 2009-09-09 23:14:36 +00:00
Chris Lattner
52651f7623 hoist the call to processDebugLoc out of the generated 
asm printer into the "printInstruction" routine.  This
fixes a problem where the experimental asmprinter would
drop debug labels in some cases, and fixes issues on ppc/xcore
where pseudo instructions like "mr" didn't get debug locs properly.

It is annoying that this moves the call from one place into each
target, but a future set of more invasive refactorings will fix
that problem.

llvm-svn: 81377
 2009-09-09 20:34:59 +00:00
Evan Cheng
91e719a6a1 Cast MO.getImm() to unsigned before comparing with an unsigned limit. 
llvm-svn: 81318
 2009-09-09 06:05:16 +00:00
Evan Cheng
95597cedfe Make sure to make stub region writable before emission, executable after emission. 
llvm-svn: 81311
 2009-09-09 01:56:29 +00:00
Evan Cheng
a0bf864b0e Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set. 
llvm-svn: 81310
 2009-09-09 01:47:07 +00:00
Evan Cheng
6c89bc0472 Remove comments which don't add much to .s readibility. 
llvm-svn: 81306
 2009-09-09 01:38:23 +00:00
Anton Korobeynikov
2b6ef7724e Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's. 
llvm-svn: 81262
 2009-09-08 22:51:43 +00:00
Anton Korobeynikov
0b3a620d60 Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and 
makes the code faster.

llvm-svn: 81220
 2009-09-08 15:22:32 +00:00
Duncan Sands
598fe699d0 Remove some not-really-used variables, as warned 
about by icc (#593, partial).  Patch by Erick Tryzelaar.

llvm-svn: 81115
 2009-09-06 12:41:19 +00:00
Duncan Sands
10c1356bad Remove some unused variables and methods warned about by 
icc (#177, partial).  Patch by Erick Tryzelaar.

llvm-svn: 81106
 2009-09-06 08:33:48 +00:00
Jim Grosbach
5a21028ece Whitespace cleanup 
llvm-svn: 80978
 2009-09-04 01:38:51 +00:00
David Goodwin
0dd9e9edb4 Calls clobber FPSCR. 
llvm-svn: 80956
 2009-09-03 22:12:28 +00:00
Evan Cheng
41e87f2f13 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. 
llvm-svn: 80904
 2009-09-03 07:04:02 +00:00
Anton Korobeynikov
7125d63acf More missed vdup patterns 
llvm-svn: 80838
 2009-09-02 21:21:28 +00:00
Sandeep Patel
9c4e094e2a Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson. 
llvm-svn: 80773
 2009-09-02 08:44:58 +00:00
Jim Grosbach
d0f70494f5 reduce size of SmallString to something more reasonable 
llvm-svn: 80710
 2009-09-01 18:55:08 +00:00
Bob Wilson
6972a16bbc Add support for generating code for vst{234}lane intrinsics. 
llvm-svn: 80707
 2009-09-01 18:51:56 +00:00
Jim Grosbach
38fc5b0277 Use raw_ostream instead of sstream 
llvm-svn: 80704
 2009-09-01 18:49:12 +00:00
David Goodwin
70557af33a RRX reads CPSR. 
llvm-svn: 80699
 2009-09-01 18:32:09 +00:00
Bob Wilson
bebadd11e4 Generate code for vld{234}_lane intrinsics. 
llvm-svn: 80656
 2009-09-01 04:26:28 +00:00
Jim Grosbach
b3c318b9d8 Fix compiler warnings 
llvm-svn: 80650
 2009-09-01 02:05:03 +00:00
Jim Grosbach
9a220088ac Clean up LSDA name generation and use for SJLJ exception handling. This 
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.

Objective C++ code could generate function names that broke the previous
scheme. This fixes that.

llvm-svn: 80649
 2009-09-01 01:57:56 +00:00
Evan Cheng
493eee1fc7 Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed. 
llvm-svn: 80615
 2009-08-31 20:14:07 +00:00
Benjamin Kramer
61232721d9 Normalize makefile comments and sort cmake file lists. 
llvm-svn: 80584
 2009-08-31 13:05:24 +00:00
Anton Korobeynikov
17529667db Add missed pattern 
llvm-svn: 80502
 2009-08-30 19:06:39 +00:00
Anton Korobeynikov
a261afbf14 EXTRACT_VECTOR_ELEMENT can have result type different from element type. 
Remove the assertion and generalize the code for ARM NEON stuff.

llvm-svn: 80498
 2009-08-30 17:14:54 +00:00
Anton Korobeynikov
b2e6f5eed4 Do not assert on too wide splats we don't support. 
llvm-svn: 80409
 2009-08-29 00:08:18 +00:00
Anton Korobeynikov
9fd6082c10 Add missed extract_element pattern 
llvm-svn: 80408
 2009-08-28 23:41:26 +00:00
Evan Cheng
d7a07ab112 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. 
llvm-svn: 80404
 2009-08-28 23:18:09 +00:00
Daniel Dunbar
0fa09bbe95 Fix -Asserts warning, round two. 
llvm-svn: 80354
 2009-08-28 08:08:22 +00:00
Evan Cheng
d53546a6cd Print a nl before pic labels so they start at a new line. This makes assembly more readable. 
llvm-svn: 80350
 2009-08-28 06:59:37 +00:00
Daniel Dunbar
1b35869d3d Fix -Asserts warning. 
llvm-svn: 80338
 2009-08-28 05:47:56 +00:00
Evan Cheng
2d5d3700e9 v4, v5 does not support sxtb / sxth. 
llvm-svn: 80322
 2009-08-28 00:31:43 +00:00
Anton Korobeynikov
c1e6083cb8 Hopefully the final missing part :( 
scalar_to_vector is fully legal now

llvm-svn: 80251
 2009-08-27 16:25:49 +00:00
Anton Korobeynikov
3aec90b4d6 Forgot about actual change :) 
llvm-svn: 80250
 2009-08-27 16:10:17 +00:00
Anton Korobeynikov
33d151e85e Transform float scalar_to_vector into subreg accesses. 
No idea whether this is profitable or not.

llvm-svn: 80245
 2009-08-27 14:38:44 +00:00
Misha Brukman
25e2b59ec6 STRD and LDRD require ARMv5TE, not just ARMv5T. 
See http://llvm.org/PR4687 for more info and links.

llvm-svn: 80244
 2009-08-27 14:14:21 +00:00
Evan Cheng
984f8efcaa Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset. 
llvm-svn: 80191
 2009-08-27 01:23:50 +00:00
Bob Wilson
5240e9de02 Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. 
The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117
 2009-08-26 17:39:53 +00:00
Anton Korobeynikov
1c904039ce Expand scalar_to_vector - we don't have any isel logic for it now 
llvm-svn: 80107
 2009-08-26 16:26:09 +00:00
Bob Wilson
02f907f33e Remove some unused SDNode definitions. 
llvm-svn: 80015
 2009-08-25 17:52:39 +00:00
Bob Wilson
d4fbf1f70a Expose the instruction contraint string as an argument to the NLdSt class. 
llvm-svn: 80011
 2009-08-25 17:46:06 +00:00
Dale Johannesen
3a5e5c7edd Make linkerprivate work for ARM and PPC. Testcase covers 
all Darwin targets; could be split into separate tests for
the chip subdirectories, but from Chris' last mail on testing
I assume he'd rather have only one test.  Generic seems to be
the best available, maybe there should be a Darwin subdirectory?

llvm-svn: 79877
 2009-08-24 01:03:42 +00:00
Chris Lattner
11f509336c remove the last uses of Config/alloca.h 
llvm-svn: 79873
 2009-08-23 22:57:38 +00:00
Benjamin Kramer
be9f477d5b Remove Streams.h from the targets. 
llvm-svn: 79853
 2009-08-23 11:52:17 +00:00
Chris Lattner
26ec3291f0 eliminate the last DOUTs from the targets. 
llvm-svn: 79833
 2009-08-23 06:49:22 +00:00
Chris Lattner
db2965c71f remove various std::ostream version of printing methods from 
MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)

llvm-svn: 79813
 2009-08-23 03:41:05 +00:00
Benjamin Kramer
52cba58070 Forgot to update some CMakeLists. 
llvm-svn: 79780
 2009-08-22 22:20:11 +00:00
Chris Lattner
8d06945fff rename TAI -> MAI, being careful not to make MAILJMP instructions :) 
llvm-svn: 79777
 2009-08-22 21:43:10 +00:00
Chris Lattner
384b7d24a9 rename COFFMCAsmInfo -> MCAsmInfoCOFF, likewise for darwin. 
llvm-svn: 79773
 2009-08-22 21:03:30 +00:00
Chris Lattner
5d8af49626 Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. 
llvm-svn: 79763
 2009-08-22 20:48:53 +00:00
Devang Patel
c071d6c1b4 Record variable debug info at ISel time directly. 
llvm-svn: 79742
 2009-08-22 17:12:53 +00:00
Eli Friedman
79615641f1 Make x86 test actually test x86 code generation. Fix the 
construct on ARM, which was breaking by coincidence, and add a similar 
testcase for ARM.

llvm-svn: 79719
 2009-08-22 03:13:10 +00:00
Bob Wilson
9482015a0a Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676
 2009-08-21 21:58:55 +00:00
Bob Wilson
6d4400e852 Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, 
now using shuffles instead of intrinsics.

llvm-svn: 79673
 2009-08-21 20:54:19 +00:00
Anton Korobeynikov
20d832fa1b Fix some typos and use type-based isel for VZIP/VUZP/VTRN 
llvm-svn: 79625
 2009-08-21 12:41:42 +00:00
Anton Korobeynikov
218db4a01c Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table. 
llvm-svn: 79624
 2009-08-21 12:41:24 +00:00
Anton Korobeynikov
220512160d Add nodes & dummy matchers for some v{zip,uzp,trn} instructions 
llvm-svn: 79622
 2009-08-21 12:40:50 +00:00
Anton Korobeynikov
dccf7cb911 Expand EXTRACT_SUBVECTOR 
llvm-svn: 79621
 2009-08-21 12:40:35 +00:00
Anton Korobeynikov
f6657d5e02 Provide vext.{16,32} 
llvm-svn: 79620
 2009-08-21 12:40:21 +00:00
Anton Korobeynikov
a2e4bc2312 Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle 
llvm-svn: 79619
 2009-08-21 12:40:07 +00:00
Bob Wilson
c046b62f1a Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as 
vector shuffles.  Temporarily remove the tests for these operations until the
new implementation is working.

llvm-svn: 79579
 2009-08-21 00:01:42 +00:00
Evan Cheng
86546fb692 Fix an obvious copy-n-paste bug. 
llvm-svn: 79535
 2009-08-20 17:01:04 +00:00
David Goodwin
d57f44783c Update Cortex-A8 instruction itineraries for integer instructions. 
llvm-svn: 79436
 2009-08-19 18:00:44 +00:00
Bob Wilson
fae9057bf0 Add support for Neon VEXT (vector extract) shuffles. 
This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428
 2009-08-19 17:03:43 +00:00
Chris Lattner
9cbc9c2d13 eliminate AsmPrinter::SwitchToSection and just have clients 
talk to the MCStreamer directly instead.

llvm-svn: 79405
 2009-08-19 05:49:37 +00:00
Jakob Stoklund Olesen
9496240bbf Simplify RegScavenger::FindUnusedReg. 
- Drop the Candidates argument and fix all callers. Now that RegScavenger
  tracks available registers accurately, there is no need to restict the
  search.
- Make sure that no aliases of the found register are in use. This was a potential bug.

llvm-svn: 79369
 2009-08-18 21:14:54 +00:00
Evan Cheng
d4d2a3d0a6 Fix revsh pattern. 
llvm-svn: 79318
 2009-08-18 05:43:23 +00:00
Benjamin Kramer
a8760e3e5a Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used after erasure. 
llvm-svn: 79189
 2009-08-16 11:56:42 +00:00
Bill Wendling
962adec4ee Reapply r79127. It was fixed by d0k. 
llvm-svn: 79136
 2009-08-15 21:21:19 +00:00
Bill Wendling
bfebbb6477 Revert r79127. It was causing compilation errors. 
llvm-svn: 79135
 2009-08-15 21:14:01 +00:00
Evan Cheng
5d841097a9 Change allowsUnalignedMemoryAccesses to take type argument since some targets 
support unaligned mem access only for certain types. (Should it be size
instead?)

ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.

llvm-svn: 79127
 2009-08-15 19:23:44 +00:00
Evan Cheng
9d351a7246 Turn on if-conversion for thumb2. 
llvm-svn: 79084
 2009-08-15 07:59:10 +00:00
Evan Cheng
cf13e0c732 Do not use frame register to reference fixed stack objects if the function is frameless. 
llvm-svn: 79067
 2009-08-15 02:05:35 +00:00
Evan Cheng
4e97ccc132 Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim. 
llvm-svn: 79039
 2009-08-14 20:48:13 +00:00
Anton Korobeynikov
3a0cde8c91 Allow targets to specify their choice of calling conventions per 
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.

Patch by Sandeep!

llvm-svn: 79033
 2009-08-14 20:10:52 +00:00
Evan Cheng
67fd47b38b Add Thumb2 lsr hooks. 
llvm-svn: 79032
 2009-08-14 20:09:37 +00:00
Evan Cheng
ebbcd00c17 80 col violation. 
llvm-svn: 79026
 2009-08-14 19:11:20 +00:00
Evan Cheng
1fa8ad98aa Indentation. 
llvm-svn: 79022
 2009-08-14 19:01:37 +00:00
Evan Cheng
7d8caa143b Also shrink immediate branches; also more assembler workarounds. 
llvm-svn: 79014
 2009-08-14 18:31:44 +00:00
Bob Wilson
80db08baec Now that all the legal Neon shuffles (or at least the ones that have been 
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.

llvm-svn: 78995
 2009-08-14 05:16:33 +00:00
Bob Wilson
d337cde6e5 Create a new ARM-specific DAG node, VDUP, to represent a splat from a 
scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.

llvm-svn: 78994
 2009-08-14 05:13:08 +00:00
Bob Wilson
7a311914ab During legalization, change Neon vdup_lane operations from shuffles to 
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993
 2009-08-14 05:08:32 +00:00
Evan Cheng
45d6a21e21 Shrink ADR and LDR from constantpool late during constantpool island pass. 
llvm-svn: 78970
 2009-08-14 00:32:16 +00:00
Evan Cheng
22969c64d0 New entry. 
llvm-svn: 78968
 2009-08-14 00:16:47 +00:00
Owen Anderson
9df206d02d Push LLVMContexts through the IntegerType APIs. 
llvm-svn: 78948
 2009-08-13 21:58:54 +00:00
Daniel Dunbar
40f904fcfb Revert 78892 and 78895, these break generating working executables on 
x86_64-apple-darwin10.

--- Reverse-merging r78895 into '.':
U    test/CodeGen/PowerPC/2008-12-12-EH.ll
U    lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U    include/llvm/Target/DarwinTargetAsmInfo.h
U    lib/Target/X86/X86TargetAsmInfo.cpp
U    lib/Target/X86/X86TargetAsmInfo.h
U    lib/Target/ARM/ARMTargetAsmInfo.h
U    lib/Target/ARM/ARMTargetMachine.cpp
U    lib/Target/ARM/ARMTargetAsmInfo.cpp
U    lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U    lib/Target/PowerPC/PPCTargetAsmInfo.h
U    lib/Target/PowerPC/PPCTargetMachine.cpp
G    lib/Target/DarwinTargetAsmInfo.cpp

llvm-svn: 78919
 2009-08-13 17:03:38 +00:00
Jim Grosbach
361b7db9bd Add missing defs of R2 and D1. 
llvm-svn: 78918
 2009-08-13 16:59:44 +00:00
David Goodwin
dd797db6bd Finalize itineraries for cortex-a8 integer multiply 
llvm-svn: 78908
 2009-08-13 15:51:13 +00:00
Jim Grosbach
6511e74282 Remove unnecessary newline 
llvm-svn: 78905
 2009-08-13 15:12:16 +00:00
Jim Grosbach
aba7f6b60b Correct comment wording 
llvm-svn: 78904
 2009-08-13 15:11:43 +00:00
Evan Cheng
8bfaf895e5 tPOP_RET now has predicate operands. 
llvm-svn: 78898
 2009-08-13 06:05:07 +00:00
Bob Wilson
e3eedf3cd2 Add a fixme message about canonicalizing floating-point vector types. 
llvm-svn: 78897
 2009-08-13 06:01:30 +00:00
Bob Wilson
8cb7da85e3 Revert r78852 for now. I want to do this differently, but I don't have time 
to fix it tonight.

llvm-svn: 78896
 2009-08-13 05:58:56 +00:00
Evan Cheng
309650d7ba It's ok to spill a tGPR register as long as it's still allocated a low register. 
llvm-svn: 78893
 2009-08-13 05:40:51 +00:00
Chris Lattner
4df533ba16 fix a minor fixme. When building with SL and later tools, the ".eh" symbols 
don't need to be exported from the .o files.

llvm-svn: 78892
 2009-08-13 05:30:22 +00:00
Bruno Cardoso Lopes
f2855aabec Change MCSectionELF to represent a section semantically instead of 
syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.

llvm-svn: 78890
 2009-08-13 05:07:35 +00:00
Bob Wilson
2940b8e9a5 Add a comment to describe why vector shuffles are legalized to custom DAG nodes. 
llvm-svn: 78884
 2009-08-13 02:13:04 +00:00
Bob Wilson
11ee30bdc8 Use cast<> instead of dyn_cast<> in places where the type is known. 
llvm-svn: 78881
 2009-08-13 01:57:47 +00:00
Dan Gohman
4b9cae5af3 Various AsmWriter output cleanups. Use WriteAsOperand instead of 
PrintUnmangledNameSafely.

llvm-svn: 78878
 2009-08-13 01:36:44 +00:00
Bob Wilson
b089d07a1f Recognize Neon VDUP shuffles during legalization instead of selection. 
llvm-svn: 78852
 2009-08-12 22:54:19 +00:00
Bob Wilson
d8b7ca4c28 Recognize Neon VREV shuffles during legalization instead of selection. 
llvm-svn: 78850
 2009-08-12 22:31:50 +00:00
Dan Gohman
bc6b14ba00 This void is implicit in C++. 
llvm-svn: 78848
 2009-08-12 22:10:57 +00:00
Bob Wilson
0cf2be2466 Generate Neon VTBL and VTBX instructions from the corresponding intrinsics. 
llvm-svn: 78835
 2009-08-12 20:51:55 +00:00
Evan Cheng
9199f62b3d PredCC is meant to be 2 bits wide, like PredCC1. 
llvm-svn: 78829
 2009-08-12 18:35:50 +00:00
David Goodwin
90e7f9873c Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
llvm-svn: 78827
 2009-08-12 18:31:53 +00:00
Jim Grosbach
74c682dde4 Add catch block handling to SjLj exception handling. 
llvm-svn: 78817
 2009-08-12 17:38:44 +00:00
Bob Wilson
61f35e39cf Fix TableGen warnings. This partly reverts my previous change to this file, 
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.

llvm-svn: 78815
 2009-08-12 17:04:56 +00:00
Jim Grosbach
77d5653945 register naming cleanup (s/ip/r12/) 
llvm-svn: 78806
 2009-08-12 15:21:13 +00:00
Chris Lattner
55df534293 Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple 
pair instead of from a virtual method on TargetMachine.  This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use 
TargetAsmInfo.

llvm-svn: 78802
 2009-08-12 07:22:17 +00:00
Evan Cheng
c369ccbe83 Shrink Thumb2 movcc instructions. 
llvm-svn: 78790
 2009-08-12 05:17:19 +00:00
Evan Cheng
bb24fe8602 Remove another Darwin assembler workaround. 
llvm-svn: 78779
 2009-08-12 02:07:19 +00:00
Evan Cheng
410447e028 80 col violation. 
llvm-svn: 78778
 2009-08-12 02:03:03 +00:00
Evan Cheng
9302c40108 Remove an Darwin assembler workaround. 
llvm-svn: 78777
 2009-08-12 01:56:42 +00:00
Evan Cheng
65f3e466df Shrink ADDS, ADC, RSB, and SUBS. 
llvm-svn: 78776
 2009-08-12 01:49:45 +00:00
Bob Wilson
00d605d359 Add missing chain operands for VLD* and VST* instructions. 
Set "mayLoad" and "mayStore" on the load/store instructions.

llvm-svn: 78761
 2009-08-12 00:49:01 +00:00
Evan Cheng
a29ee9f509 Shrinkify Thumb2 r = add sp, imm. 
llvm-svn: 78745
 2009-08-11 23:00:31 +00:00
Chris Lattner
a74023896f Change the asmprinter to print the comment character before the 
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character.  This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character.  This also allows hoisting the darwin stuff up to the
shared TAI class.

llvm-svn: 78737
 2009-08-11 22:39:40 +00:00
David Goodwin
2686178489 Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter. 
llvm-svn: 78736
 2009-08-11 22:38:43 +00:00
Chris Lattner
f27d5f6662 factorize more darwin TAI stuff. Note that this gives 
darwin/arm support for .no_dead_strip

llvm-svn: 78734
 2009-08-11 22:31:42 +00:00
Chris Lattner
7015f75b6a factorize darwin ProtectedDirective and SetDirective. 
llvm-svn: 78732
 2009-08-11 22:22:44 +00:00
Chris Lattner
bf7a1a3e38 all darwin targets have .space and .zerofill, pull up. 
llvm-svn: 78730
 2009-08-11 22:17:31 +00:00
Chris Lattner
44a2fda8c1 eliminate template from arm TAI 
llvm-svn: 78729
 2009-08-11 22:14:59 +00:00
Chris Lattner
8c7eb509d3 move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate 
template in PPC backend for TAI.

llvm-svn: 78727
 2009-08-11 22:06:07 +00:00
Evan Cheng
783028063e Shrinkify Thumb2 load / store multiple instructions. 
llvm-svn: 78717
 2009-08-11 21:11:32 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Chris Lattner
30d9c39337 pass the TargetTriple down from each target ctor to the 
LLVMTargetMachine ctor.  It is currently unused.

llvm-svn: 78711
 2009-08-11 20:42:37 +00:00
Chris Lattner
45bdc96988 split "JumpTableDirective" (an existing hack) into a PIC and nonPIC 
version.  This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.

The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.

llvm-svn: 78709
 2009-08-11 20:30:58 +00:00
Jim Grosbach
67841ae0a8 Add Thumb2 eh_sjlj_setjmp implementation 
llvm-svn: 78701
 2009-08-11 19:42:21 +00:00
Jim Grosbach
c80da41574 fix GetInstSizeInBytes for eh_sjlj_setjmp 
llvm-svn: 78683
 2009-08-11 17:08:15 +00:00
Benjamin Kramer
0481803d2a This void is implicit in C++. 
llvm-svn: 78678
 2009-08-11 16:03:08 +00:00
Jim Grosbach
3c898a99bd Whitespace cleanup. Remove trailing whitespace. 
llvm-svn: 78666
 2009-08-11 15:33:49 +00:00
Jim Grosbach
d5fc7e81b2 Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header. 
llvm-svn: 78665
 2009-08-11 15:26:27 +00:00
Evan Cheng
249f07cf57 Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions. 
llvm-svn: 78659
 2009-08-11 09:37:40 +00:00
Evan Cheng
434a66fa9b Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to 
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.

llvm-svn: 78658
 2009-08-11 08:52:18 +00:00
Evan Cheng
9fdf9b4435 80 column violation. 
llvm-svn: 78657
 2009-08-11 08:47:46 +00:00
Evan Cheng
766c076bea Cosmetic changes. 
llvm-svn: 78655
 2009-08-11 07:36:14 +00:00
Evan Cheng
dbccf353d1 Adding a blank line back. 
llvm-svn: 78654
 2009-08-11 07:32:58 +00:00
Bob Wilson
d64e304671 Use vAny type to get rid of Neon intrinsics that differed only in whether 
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646
 2009-08-11 05:39:44 +00:00
Bob Wilson
1c75a23299 Use new EVT::vAny type to combine Neon intrinsics for VPADD. 
llvm-svn: 78632
 2009-08-11 01:15:26 +00:00
David Goodwin
8ca187462c Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings. 
llvm-svn: 78629
 2009-08-11 01:07:38 +00:00
Jim Grosbach
c2fd915309 Add stdlib.h 
llvm-svn: 78627
 2009-08-11 00:20:00 +00:00
Jim Grosbach
c9a1dd9291 SjLj based exception handling unwinding support. This patch is nasty, brutish 
and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625
 2009-08-11 00:09:57 +00:00