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233992bc56
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234 Commits

Author SHA1 Message Date
Bob Wilson
233992bc56 Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Bob Wilson
0159d0d864 Clean up some unnecessary initializations. 
llvm-svn: 83566
 2009-10-08 18:52:56 +00:00
Bob Wilson
c62c9946e2 Clean up a comment (indentation was wrong). 
llvm-svn: 83565
 2009-10-08 18:51:31 +00:00
Bob Wilson
276bdabb9a Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83526
 2009-10-08 05:18:18 +00:00
Bob Wilson
8aa1d328b5 Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83518
 2009-10-08 00:28:28 +00:00
Bob Wilson
958e4ae815 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83513
 2009-10-08 00:21:01 +00:00
Bob Wilson
729cd181a2 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83508
 2009-10-07 23:54:04 +00:00
Bob Wilson
3cbf156518 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83506
 2009-10-07 23:39:57 +00:00
Bob Wilson
0ffa9679a5 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83502
 2009-10-07 22:57:01 +00:00
Bob Wilson
cee91108da Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
llvm-svn: 83486
 2009-10-07 20:49:18 +00:00
Bob Wilson
af14187764 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
llvm-svn: 83484
 2009-10-07 20:30:08 +00:00
Bob Wilson
62a3e55cea Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
llvm-svn: 83482
 2009-10-07 18:47:39 +00:00
Bob Wilson
9bb47b3e5d Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
llvm-svn: 83479
 2009-10-07 18:09:32 +00:00
Bob Wilson
b38401ccef Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
llvm-svn: 83471
 2009-10-07 17:24:55 +00:00
Bob Wilson
a77f6a7814 Rearrange code for selecting vld2 intrinsics. No functionality change. 
This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470
 2009-10-07 17:23:09 +00:00
Bob Wilson
8cd1ea81c4 Add codegen support for NEON vld2 operations on quad registers. 
llvm-svn: 83422
 2009-10-06 22:01:59 +00:00
Bob Wilson
bbcf30c05c Pass the optimization level when constructing the ARM instruction selector. 
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988
 2009-09-28 14:30:20 +00:00
Anton Korobeynikov
189ce11684 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. 
This should be better than single load from constpool.

llvm-svn: 82948
 2009-09-27 23:52:58 +00:00
Dan Gohman
0c4e55a2f8 Rename getTargetNode to getMachineNode, for consistency with the 
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790
 2009-09-25 18:54:59 +00:00
Bob Wilson
6972a16bbc Add support for generating code for vst{234}lane intrinsics. 
llvm-svn: 80707
 2009-09-01 18:51:56 +00:00
Bob Wilson
bebadd11e4 Generate code for vld{234}_lane intrinsics. 
llvm-svn: 80656
 2009-09-01 04:26:28 +00:00
Bob Wilson
5240e9de02 Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. 
The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117
 2009-08-26 17:39:53 +00:00
Devang Patel
c071d6c1b4 Record variable debug info at ISel time directly. 
llvm-svn: 79742
 2009-08-22 17:12:53 +00:00
Anton Korobeynikov
20d832fa1b Fix some typos and use type-based isel for VZIP/VUZP/VTRN 
llvm-svn: 79625
 2009-08-21 12:41:42 +00:00
Anton Korobeynikov
220512160d Add nodes & dummy matchers for some v{zip,uzp,trn} instructions 
llvm-svn: 79622
 2009-08-21 12:40:50 +00:00
Bob Wilson
c046b62f1a Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as 
vector shuffles.  Temporarily remove the tests for these operations until the
new implementation is working.

llvm-svn: 79579
 2009-08-21 00:01:42 +00:00
Evan Cheng
1fa8ad98aa Indentation. 
llvm-svn: 79022
 2009-08-14 19:01:37 +00:00
Bob Wilson
7a311914ab During legalization, change Neon vdup_lane operations from shuffles to 
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993
 2009-08-14 05:08:32 +00:00
Owen Anderson
9df206d02d Push LLVMContexts through the IntegerType APIs. 
llvm-svn: 78948
 2009-08-13 21:58:54 +00:00
Evan Cheng
c369ccbe83 Shrink Thumb2 movcc instructions. 
llvm-svn: 78790
 2009-08-12 05:17:19 +00:00
Bob Wilson
00d605d359 Add missing chain operands for VLD* and VST* instructions. 
Set "mayLoad" and "mayStore" on the load/store instructions.

llvm-svn: 78761
 2009-08-12 00:49:01 +00:00
Evan Cheng
a29ee9f509 Shrinkify Thumb2 r = add sp, imm. 
llvm-svn: 78745
 2009-08-11 23:00:31 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Jim Grosbach
3c898a99bd Whitespace cleanup. Remove trailing whitespace. 
llvm-svn: 78666
 2009-08-11 15:33:49 +00:00
Evan Cheng
434a66fa9b Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to 
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.

llvm-svn: 78658
 2009-08-11 08:52:18 +00:00
Bob Wilson
d64e304671 Use vAny type to get rid of Neon intrinsics that differed only in whether 
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646
 2009-08-11 05:39:44 +00:00
Dan Gohman
888bcd3483 Fix a bug where DAGCombine was producing an illegal ConstantFP 
node after legalize, and remove the workaround code from the
ARM backend.

llvm-svn: 78615
 2009-08-10 23:15:10 +00:00
Owen Anderson
b4bce99769 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Evan Cheng
f0bb0f5204 Handle the constantfp created during post-legalization dag combiner phase. 
llvm-svn: 78594
 2009-08-10 20:25:59 +00:00
Anton Korobeynikov
ae22c37afb Use VLDM / VSTM to spill/reload 128-bit Neon registers 
llvm-svn: 78468
 2009-08-08 13:35:48 +00:00
Bob Wilson
88fafd84ea Implement Neon VZIP and VUZP instructions. These are very similar to VTRN, 
so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460
 2009-08-08 06:13:25 +00:00
Bob Wilson
935ee0c122 Implement Neon VTRN instructions. For now, anyway, these are selected 
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459
 2009-08-08 05:53:00 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00
Bob Wilson
bd7627b23e Implement Neon VST[234] operations. 
llvm-svn: 78330
 2009-08-06 18:47:44 +00:00
Bob Wilson
905678ab37 Neon does not actually have VLD{234}.64 instructions. 
These operations will have to be synthesized from other instructions.

llvm-svn: 78263
 2009-08-06 00:24:27 +00:00
Bob Wilson
1fe51064ba Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. 
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.

llvm-svn: 78136
 2009-08-05 00:49:09 +00:00
Bob Wilson
eb3b616a7e Lower CONCAT_VECTOR during legalization instead of matching it during isel. 
Add a testcase.

llvm-svn: 77992
 2009-08-03 20:36:38 +00:00