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Commit Graph

81901 Commits

Author SHA1 Message Date
Preston Gurd
237e411bb4 Trivial change to make the test use -mcpu=generic so as to avoid
a failure if run on an Intel Atom with post RA instruction scheduling.

llvm-svn: 155587
2012-04-25 21:04:54 +00:00
Benjamin Kramer
36acdd4832 Reapply the SmallMap patch with a fix.
Comparing ~0UL with an unsigned will always return false when long is 64 bits long.

llvm-svn: 155568
2012-04-25 18:01:58 +00:00
Jakob Stoklund Olesen
e2913e1ad5 Print IV chain numbers while collecting them.
llvm-svn: 155567
2012-04-25 18:01:32 +00:00
Jakob Stoklund Olesen
24c99d2966 Remove more dead code.
llvm-svn: 155566
2012-04-25 18:01:30 +00:00
Richard Barton
e9a972bbe3 Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation.
llvm-svn: 155565
2012-04-25 18:00:18 +00:00
Eric Christopher
d38d9bb28b Revert "First implementation of:"
This reverts commit 76271a3366731d4c372fdebcd8d3437e6e09a61b.

as it's breaking the bots.

llvm-svn: 155562
2012-04-25 17:51:00 +00:00
Stepan Dyatkovskiy
a580659b6c First implementation of:
- FlatArrayMap. Very simple map container that uses flat array inside.
- MultiImplMap. Map container interface, that has two modes, one for small amount of elements and one for big amount.
- SmallMap. SmallMap is DenseMap compatible MultiImplMap. It uses FlatArrayMap for small mode, and DenseMap for big mode. 

Also added unittests for new classes and update for ProgrammersManual.
For more details about new classes see ProgrammersManual and comments in sourcecode.

llvm-svn: 155557
2012-04-25 17:09:38 +00:00
Jakob Stoklund Olesen
d8587c363b Simplify LiveIntervals::getApproximateInstructionCount().
This function is only used for a heuristic during -join-physregs. It
doesn't need floating point.

llvm-svn: 155554
2012-04-25 16:32:23 +00:00
Jakob Stoklund Olesen
dbd5f4eb96 Remove a dead function.
llvm-svn: 155553
2012-04-25 16:32:20 +00:00
Jakob Stoklund Olesen
7f1be74a4a Remove the -disable-cross-class-join option.
Cross-class joins have been normal and fully supported for a while now.
With TableGen generating the getMatchingSuperRegClass() hook, they are
unlikely to cause problems again.

llvm-svn: 155552
2012-04-25 16:17:50 +00:00
Jakob Stoklund Olesen
b8d98c5060 Cross-class joining is winning.
Remove the heuristic for disabling cross-class joins. The greedy
register allocator can handle the narrow register classes, and when it
splits a live range, it can pick a larger register class.

Benchmarks were unaffected by this change.

<rdar://problem/11302212>

llvm-svn: 155551
2012-04-25 16:17:47 +00:00
Craig Topper
5828c654b9 Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning.
llvm-svn: 155538
2012-04-25 06:56:34 +00:00
Craig Topper
1a016fd95d Use vector_shuffles instead of target specific unpack nodes for AVX ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code.
llvm-svn: 155537
2012-04-25 06:39:39 +00:00
Chris Lattner
f492d85ae9 openbsd doesn't support soname, patch by Brad Smith!
llvm-svn: 155536
2012-04-25 06:37:20 +00:00
Chandler Carruth
8821a79947 Actually delete now-empty file.
llvm-svn: 155532
2012-04-25 02:30:00 +00:00
Lang Hames
7f69fbca29 Reverting r155468. Chris and Chandler have convinced me that it's dangerous and
in poor taste.

Talking through some alternate solutions with Chandler.

llvm-svn: 155530
2012-04-25 02:16:54 +00:00
Akira Hatanaka
b3ecf903f1 Do not use $gp as a dedicated global register if the target ABI is not O32.
llvm-svn: 155522
2012-04-25 01:24:52 +00:00
Andrew Trick
f76f2597a3 typo in declaration from earlier today
llvm-svn: 155519
2012-04-25 01:11:22 +00:00
Dan Gohman
64171a0b3b Simplify the known retain count tracking; use a boolean state instead
of a precise count. Also, move RRInfo's Partial field into PtrState,
now that it won't increase the size.

llvm-svn: 155513
2012-04-25 00:50:46 +00:00
Dan Gohman
3a24d34041 Build custom predecessor and successor lists for each basic block.
These lists exclude invoke unwind edges and loop backedges which
are being ignored. This makes it easier to ignore them
consistently.

llvm-svn: 155500
2012-04-24 22:53:18 +00:00
Jim Grosbach
7ac2ac85a8 ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.

rdar://11257547

llvm-svn: 155499
2012-04-24 22:40:08 +00:00
Andrew Trick
47f01c373e Fix a naughty header include that breaks "installed" builds.
llvm-svn: 155486
2012-04-24 20:36:19 +00:00
Nadav Rotem
3c817bb807 ConstantFoldSelectInstruction swapped the operands of the select.
Fix 12592. Patch by Matt Pharr.

llvm-svn: 155480
2012-04-24 20:18:49 +00:00
Nadav Rotem
62a0eeb276 Fix the testcase. We do expect two vblendw on XMMs.
llvm-svn: 155477
2012-04-24 19:57:38 +00:00
Nadav Rotem
d35ec2e4ad Add a testcase for 155440
llvm-svn: 155475
2012-04-24 19:45:28 +00:00
Evan Cheng
7f9bf43bcf MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and refuse to break edge to EH landing pad. rdar://11300144
llvm-svn: 155470
2012-04-24 19:06:55 +00:00
Lang Hames
08eb5f2340 Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. This fixes
<rdar://problem/11291436>.

llvm-svn: 155468
2012-04-24 18:58:36 +00:00
Chandler Carruth
eb9c5df516 Fix a crash on valid (if UB) bitcode that is produced for some global
constants in C++11 mode. I have no idea why it required such particular
circumstances to get here, the code seems clearly to rely upon unchecked
assumptions.

Specifically, when we decide to form an index into a struct type, we may
have gone through (at least one) zero-length array indexing round, which
would have left the offset un-adjusted, and thus not necessarily valid
for use when indexing the struct type.

This is just an canonicalization step, so the correct thing is to refuse
to canonicalize nonsensical GEPs of this form. Implemented, and test
case added.

Fixes PR12642. Pair debugged and coded with Richard Smith. =] I credit
him with most of the debugging, and preventing me from writing the wrong
code.

llvm-svn: 155466
2012-04-24 18:42:47 +00:00
Jim Grosbach
69d9654f7c ARM: Nuke remnant bogus code.
r154362 was supposed to delete this bit, but obviously didn't.

rdar://11305594

llvm-svn: 155465
2012-04-24 18:39:47 +00:00
Stepan Dyatkovskiy
37fad66b80 Related to PR1255. Let's begin. I'll commit classes that corresponds to our latest PR1255 discussion posts in llvm-commits.
Strategy.
0. Implement new classes. Classes doesn't affect anything. They still work with ConstantInt base values at this stage.
1. Fictitious replacement of current ConstantInt case values with ConstantRangesSet. Case ranges set will still hold single value, and ConstantInt *getCaseValue() will return it. But additionally implement new method in SwitchInst that allows to work with case ranges. Currenly I think it should be some wrapper that returns either single value or ConstantRangesSet object.
2. Step-by-step replacement of old "ConstantInt* getCaseValue()" with new alternative. Modify algorithms for all passes that works with SwitchInst. But don't modify LLParser and BitcodeReader/Writer. Still hold single value in each ConstantRangesSet object. On this stage some parts of LLVM will use old-style methods, and some ones new-style.
3. After all getCaseValue() usages will removed and whole LLVM and its clients will work in new style - modify LLParser, Reader and Writer. Remove getCaseValue().
4. Replace ConstantInt*-based case ranges set items with APInt ones.

Currently we are on Zero Stage: New classes.
ConstantRangesSet.
I selected ConstantArrays as case ranges set "holder" object (it is a temporary decision, I'll explain why below). The array items are may be ConstantVectors with single item, and ConstantVectors with two items (that means single number and range respectively).
The ConstantInt will used as basic value representation. It will replaced with APInt then. Of course ConstantArray and ConstantVector will go away after ConstantInt => APInt replacement.

New class mandatory features:
- bool isSatisfies(ConstantInt *V) method (need better name?). Returns true if the given value satisfies this case.
- Case's ranges and values enumeration. In some passes we need to analize each case (SwitchLowering for example).

Factory + unified clusterify.
I also propose to implement the factory that allows to build case object with user friendly way. I called it CRSBuilder by now.
Currenly I implemented the factory that allows add,remove pairs of range+successor. It also allows add existing ConstantRangesSet decompiling it to separated ranges. Factory can emit either clusters set (single case range + successor) or the set of "ConstantRangesSet + Successor" pairs.
So you can use it either as builder for new cases set for SwitchInst, or for clusterification of existing cases set.
Just call Factory.optimize() and it emits optimized and sorted clusters collection for you!
I tested clusterification on SelectionDAGBuilder - it works fine. Don't worry it was not included in this patch. Just new classes.
Factory is a template. There are two params: SuccessorClass and IsReadonly. So you can specify what successor you need (BB or MBB). And you can also restrict your factory to use values in read-only mode (SelectionDAGBuilder need IsReadonly=true). Read-only factory couldn't build the cases ranges.

llvm-svn: 155464
2012-04-24 18:31:10 +00:00
Nadav Rotem
021d75713c AVX: Add additional vbroadcast replacement sequences for integers.
Remove the v2f64 patterns because it does not match any vbroadcast
instruction.

llvm-svn: 155461
2012-04-24 18:09:59 +00:00
Andrew Trick
b18b7c6e55 cmake: new file
llvm-svn: 155460
2012-04-24 18:06:49 +00:00
Andrew Trick
4c57a9bcf1 misched: DAG builder must special case earlyclobber
llvm-svn: 155459
2012-04-24 18:04:41 +00:00
Andrew Trick
0b0b66833e misched: try (not too hard) to place debug values where they belong
llvm-svn: 155458
2012-04-24 18:04:37 +00:00
Andrew Trick
02daf554b7 misched: ignore debug values during scheduling
llvm-svn: 155457
2012-04-24 18:04:34 +00:00
Andrew Trick
cc1e9fe38e misched: DAG builder support for tracking register pressure within the current scheduling region.
The DAG builder is a convenient place to do it. Hopefully this is more
efficient than a separate traversal over the same region.

llvm-svn: 155456
2012-04-24 17:56:43 +00:00
Andrew Trick
61df7b36e9 RegisterPressure: A utility for computing register pressure within a
MachineInstr sequence.

This uses the new target interface for tracking register pressure
using pressure sets to model overlapping register classes and
subregisters.

RegisterPressure results can be tracked incrementally or stored at
region boundaries. Global register pressure can be deduced from local
RegisterPressure results if desired.

This is an early, somewhat untested implementation. I'm working on
testing it within the context of a register pressure reducing
MachineScheduler.

llvm-svn: 155454
2012-04-24 17:53:35 +00:00
Kevin Enderby
f954efdbea Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
instructions.

llvm-svn: 155453
2012-04-24 17:45:56 +00:00
Kevin Enderby
e7378cb42d Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)
instructions.

llvm-svn: 155444
2012-04-24 15:55:00 +00:00
Nadav Rotem
f2756d7e7f AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8
immediate. We can't use it here because the shuffle code does not check that
the lower part of the word is identical to the upper part.

llvm-svn: 155440
2012-04-24 11:27:53 +00:00
Richard Barton
543457a8c8 Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector
llvm-svn: 155439
2012-04-24 11:13:20 +00:00
Nadav Rotem
d060c25823 AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions
using the pattern (vbroadcast (i32load src)). In some cases, after we generate
this pattern new users are added to the load node, which prevent the selection
of the blend pattern. This commit provides fallback patterns which perform
in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1).

llvm-svn: 155437
2012-04-24 11:07:03 +00:00
Bill Wendling
a9402cc275 Look for the 'Is Simulated' module flag. This indicates that the program is compiled to run on a simulator.
llvm-svn: 155435
2012-04-24 11:03:50 +00:00
Bill Wendling
9f736e7c65 FileCheck-ize tests.
llvm-svn: 155434
2012-04-24 10:45:44 +00:00
Bill Wendling
6824095c62 FileCheck-ize these tests.
llvm-svn: 155433
2012-04-24 10:36:42 +00:00
Bill Wendling
b394f59f17 FileCheck-ize these tests. Harden some of them.
llvm-svn: 155432
2012-04-24 09:15:38 +00:00
Craig Topper
dae7196823 Remove dangling spaces. Fix some other formatting.
llvm-svn: 155429
2012-04-24 06:36:35 +00:00
Craig Topper
61065e271e Simplify code a bit and make it compile better. Remove unused parameters.
llvm-svn: 155428
2012-04-24 06:02:29 +00:00
Evan Cheng
addf0dcf31 Add a missing cpu subtype.
llvm-svn: 155402
2012-04-23 22:41:39 +00:00
Jim Grosbach
66edf44403 Tidy up. 80 columns, whitespace, et. al.
llvm-svn: 155399
2012-04-23 22:04:10 +00:00