Akira Hatanaka
23c5cb5daf
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
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llvm-svn: 144370
2011-11-11 04:06:38 +00:00
Pete Cooper
224434deec
Added invariant field to the DAG.getLoad method and changed all calls.
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When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
Akira Hatanaka
f71673c585
Make changes necessary in LowerFormalArguments to support Mips64.
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llvm-svn: 143218
2011-10-28 19:55:48 +00:00
Akira Hatanaka
3069ec27da
Make changes necessary in LowerCall to support Mips64.
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llvm-svn: 143217
2011-10-28 19:49:00 +00:00
Akira Hatanaka
856f4e30b2
Add variable IsO32 to MipsTargetLowering.
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llvm-svn: 143213
2011-10-28 18:47:24 +00:00
Eli Friedman
f43710f4a8
Fix misc warnings. Patch by Joe Abbey.
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llvm-svn: 142332
2011-10-18 03:17:34 +00:00
Akira Hatanaka
4939842b5a
Add definitions of conditional moves with 64-bit operands. Comment out code for
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expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
Akira Hatanaka
3f89f9bc37
Modify lowering of GlobalAddress so that correct code is emitted when target is
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Mips64.
llvm-svn: 141618
2011-10-11 00:55:05 +00:00
Akira Hatanaka
404fb72f59
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
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zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
Akira Hatanaka
6c6ff6fde7
Add support for 64-bit divide instructions.
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llvm-svn: 141024
2011-10-03 21:06:13 +00:00
Akira Hatanaka
c9268767d6
Add definitions of Mips64 rotate instructions.
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llvm-svn: 140870
2011-09-30 18:51:46 +00:00
Akira Hatanaka
a641d087fc
Set register class of a register according to value of HasMips64.
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llvm-svn: 140570
2011-09-26 21:55:17 +00:00
Akira Hatanaka
37493224a9
Define variable HasMips64 in MipsTargetLowering.
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llvm-svn: 140569
2011-09-26 21:47:02 +00:00
Akira Hatanaka
9db31c430a
In single float mode, double precision FP arguments are passed in integer
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registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
Akira Hatanaka
bf382ce7ed
Preparation for adding simple Mips64 instructions.
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llvm-svn: 140443
2011-09-24 01:34:44 +00:00
Akira Hatanaka
8573d26722
Make FGR64RegisterClass available if target is Mips64.
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llvm-svn: 140397
2011-09-23 18:28:39 +00:00
Akira Hatanaka
f213002a1c
Do not rely on the enum values of argument registers A0-A3 being consecutive.
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Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
llvm-svn: 140363
2011-09-23 00:58:33 +00:00
Akira Hatanaka
60cd2b0c2f
Remove unnecessary condition check.
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llvm-svn: 140291
2011-09-22 02:41:29 +00:00
Akira Hatanaka
eb3e16d39f
Change the names of functions isMips* to hasMips*.
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llvm-svn: 140214
2011-09-20 23:53:09 +00:00
Akira Hatanaka
6731be3175
Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't
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yet legal according to comments in LegalizeDAG.cpp:227.
Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.
The two failing tests reported in PR10876 pass after applying this patch.
llvm-svn: 140046
2011-09-19 20:26:02 +00:00
Duncan Sands
d1311488fe
Add codegen support for vector select (in the IR this means a select
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with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
2011-09-06 19:07:46 +00:00
Eli Friedman
6d27cb5e01
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
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llvm-svn: 138751
2011-08-29 18:23:02 +00:00
Akira Hatanaka
02cff5ae2d
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
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needed for Mips32.
llvm-svn: 138132
2011-08-19 22:59:00 +00:00
Akira Hatanaka
163382894e
Use subword loads instead of a 4-byte load when the size of a structure (or a
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piece of it) that is being passed by value is smaller than a word.
llvm-svn: 138007
2011-08-18 23:39:37 +00:00
Akira Hatanaka
1876aadea7
Make IsShiftedMask a static function rather than defining it in an
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anonymous namespace.
llvm-svn: 137975
2011-08-18 20:07:42 +00:00
Akira Hatanaka
0af1edcce0
Changed definition of EXT and INS per Bruno's comments.
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llvm-svn: 137892
2011-08-17 22:59:46 +00:00
Akira Hatanaka
6eb513003d
Add support for half-word unaligned loads and stores.
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llvm-svn: 137848
2011-08-17 18:49:18 +00:00
Akira Hatanaka
60ccc76576
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
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llvm-svn: 137831
2011-08-17 17:45:08 +00:00
Akira Hatanaka
0179c7fa68
Add support for ext and ins.
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llvm-svn: 137804
2011-08-17 02:05:42 +00:00
Akira Hatanaka
c9c0190cbe
Define unaligned load and store.
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llvm-svn: 137515
2011-08-12 21:30:06 +00:00
Eli Friedman
afd08dcc2c
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
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I think this completes the basic CodeGen for atomicrmw and cmpxchg.
llvm-svn: 136813
2011-08-03 21:06:02 +00:00
Eli Friedman
842ea169de
Code generation for 'fence' instruction.
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llvm-svn: 136283
2011-07-27 22:21:52 +00:00
Akira Hatanaka
a50bbdfe15
Lower memory barriers to sync instructions.
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llvm-svn: 135537
2011-07-19 23:30:50 +00:00
Akira Hatanaka
cccc5fca34
Change variable name.
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llvm-svn: 135522
2011-07-19 20:56:53 +00:00
Akira Hatanaka
14e517df43
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
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ANDi, when the instruction does not have any immediate operands.
llvm-svn: 135520
2011-07-19 20:34:00 +00:00
Akira Hatanaka
b4db39fa83
Use descriptive variable names.
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llvm-svn: 135514
2011-07-19 20:11:17 +00:00
Akira Hatanaka
19c16a84ff
Fix comments.
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llvm-svn: 135496
2011-07-19 18:19:40 +00:00
Akira Hatanaka
f59cbeec14
Remove redundant instructions.
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- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
instruction being expanded, instead of masking it in thisMBB.
- Remove redundant Or in EmitAtomicCmpSwap.
llvm-svn: 135495
2011-07-19 18:14:26 +00:00
Akira Hatanaka
57d207bc7b
Separate code that modifies control flow from code that adds instruction to
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basic blocks.
llvm-svn: 135490
2011-07-19 17:09:53 +00:00
Akira Hatanaka
ad3687eb3a
Make EmitAtomic functions return the correct MachineBasicBlocks so that
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ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.
llvm-svn: 135465
2011-07-19 03:42:13 +00:00
Akira Hatanaka
55b8d79a52
Do not insert instructions in reverse order.
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llvm-svn: 135464
2011-07-19 03:14:58 +00:00
Akira Hatanaka
52263f51f1
Do not treat atomic.load.sub differently than other atomic binary intrinsics.
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llvm-svn: 135418
2011-07-18 19:58:59 +00:00
Akira Hatanaka
79f38f0ae7
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
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moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
Akira Hatanaka
d5690b20d3
Change destination register operands of SC instructions so that unique
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virtual registers are used.
llvm-svn: 135403
2011-07-18 17:44:27 +00:00
Chris Lattner
e1fe7061ce
land David Blaikie's patch to de-constify Type, with a few tweaks.
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llvm-svn: 135375
2011-07-18 04:54:35 +00:00
Cameron Zwarich
c23366d357
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
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is to use this for architectures that have a native FMA instruction.
llvm-svn: 134742
2011-07-08 21:39:21 +00:00
Akira Hatanaka
90fcf55a54
Lower MachineInstr to MC Inst and print to .s files.
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llvm-svn: 134661
2011-07-07 23:56:50 +00:00
Akira Hatanaka
d3c031eb00
Reverse order of operands of address operand mem so that the base operand comes
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before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134625
2011-07-07 18:57:00 +00:00
Eric Christopher
f04ac137f3
Update comment for getRegForInlineAsmConstraint for Mips.
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llvm-svn: 134087
2011-06-29 19:33:04 +00:00
Eric Christopher
82c3bcfb14
Remove getRegClassForInlineAsmConstraint for Mips.
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Part of rdar://9643582
llvm-svn: 134084
2011-06-29 19:04:31 +00:00