James Molloy
85be8f7f88
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
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llvm-svn: 150169
2012-02-09 10:56:31 +00:00
Kevin Enderby
cb876a7560
Fixed a crash in llvm-mc for Mach-O when a symbol difference expression uses a
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symbol from an assignment. In this case the symbol did not have a fragment so
MCObjectWriter::IsSymbolRefDifferenceFullyResolved() should not have been
calling IsSymbolRefDifferenceFullyResolvedImpl() with a NULL fragment and should
just have returned false in that case.
llvm-svn: 149442
2012-01-31 23:02:57 +00:00
Devang Patel
be1817e3e0
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
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llvm-svn: 149291
2012-01-30 22:47:12 +00:00
Devang Patel
a5bfdedb9f
Intel syntax. Support .intel_syntax directive.
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llvm-svn: 149270
2012-01-30 20:02:42 +00:00
James Molloy
b586b7c9c7
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
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Fixes PR11877
llvm-svn: 149180
2012-01-28 15:58:32 +00:00
Rafael Espindola
c74f450f77
Small improvement to the recursion detection logic from the previous commit.
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llvm-svn: 149175
2012-01-28 06:22:14 +00:00
Rafael Espindola
82e15e4544
Handle recursive variable definitions directly. This gives us better error
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messages and allows us to fix PR11865.
llvm-svn: 149174
2012-01-28 05:57:00 +00:00
Devang Patel
e4725ba181
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
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llvm-svn: 149142
2012-01-27 19:48:28 +00:00
James Molloy
402abeda73
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
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This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
llvm-svn: 149057
2012-01-26 09:25:43 +00:00
Jim Grosbach
20a6580dff
ARM assemly parsing and validation of IT instruction.
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"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
llvm-svn: 148969
2012-01-25 19:52:01 +00:00
Jim Grosbach
e8095f3b49
NEON VLD4(all lanes) assembly parsing and encoding.
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llvm-svn: 148884
2012-01-25 00:01:08 +00:00
Jim Grosbach
f478b2a706
NEON VLD3(all lanes) assembly parsing and encoding.
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llvm-svn: 148882
2012-01-24 23:47:04 +00:00
Jim Grosbach
012239e10a
ARM Darwin symbol ref differences w/o subsection-via-symbols.
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When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.
llvm-svn: 148865
2012-01-24 21:45:25 +00:00
Devang Patel
0da753c9e6
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
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llvm-svn: 148864
2012-01-24 21:43:36 +00:00
Jim Grosbach
e151b15949
NEON VST4(one lane) assembly parsing and encoding.
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llvm-svn: 148836
2012-01-24 18:53:13 +00:00
Jim Grosbach
a78348fcda
NEON VLD4(one lane) assembly parsing and encoding.
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llvm-svn: 148832
2012-01-24 18:37:25 +00:00
Jim Grosbach
f3607eac5d
NEON Two-operand assembly aliases for VSRA.
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llvm-svn: 148821
2012-01-24 17:55:36 +00:00
Jim Grosbach
47f7ce80b8
Remove redundant test file.
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llvm-svn: 148820
2012-01-24 17:55:32 +00:00
Jim Grosbach
630dd380c7
NEON Two-operand assembly aliases for VSLI.
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llvm-svn: 148819
2012-01-24 17:49:15 +00:00
Jim Grosbach
42c0f99aa0
NEON Two-operand assembly aliases for VSRI.
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llvm-svn: 148818
2012-01-24 17:46:58 +00:00
Jim Grosbach
703b0bb646
Tidy up.
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llvm-svn: 148817
2012-01-24 17:46:54 +00:00
Jim Grosbach
3be662b372
NEON VST4(multiple 4 element structures) assembly parsing.
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llvm-svn: 148764
2012-01-24 00:58:13 +00:00
Jim Grosbach
ca32a49eb5
NEON VLD4(multiple 4 element structures) assembly parsing.
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llvm-svn: 148762
2012-01-24 00:43:17 +00:00
Jim Grosbach
a4687dcf5a
NEON VST3(single element from one lane) assembly parsing.
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llvm-svn: 148755
2012-01-24 00:07:41 +00:00
Jim Grosbach
048162ddf9
NEON VST3(multiple 3-element structures) assembly parsing.
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llvm-svn: 148748
2012-01-23 23:45:44 +00:00
Jim Grosbach
8035fac461
NEON VLD3(multiple 3-element structures) assembly parsing.
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llvm-svn: 148745
2012-01-23 23:20:46 +00:00
Devang Patel
327773a25b
Intel syntax: Robustify parsing of memory operand's displacement experssion.
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llvm-svn: 148737
2012-01-23 22:35:25 +00:00
Jim Grosbach
dd667a11d3
NEON VLD3 lane-indexed assembly parsing and encoding.
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llvm-svn: 148734
2012-01-23 21:53:26 +00:00
Rafael Espindola
9f3a003d3c
Add support for .cfi_signal_frame. Fixes pr11762.
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llvm-svn: 148733
2012-01-23 21:51:52 +00:00
Devang Patel
3c6289f43a
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
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llvm-svn: 148721
2012-01-23 20:20:06 +00:00
Jim Grosbach
0eeacbfe2e
Simplify some NEON assembly pseudo definitions.
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Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
llvm-svn: 148718
2012-01-23 19:39:08 +00:00
Devang Patel
9698de5bf3
Intel syntax: Parse segment registers.
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llvm-svn: 148712
2012-01-23 18:31:58 +00:00
Devang Patel
0ecda3fc14
Intel syntax: Robustify register parsing.
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llvm-svn: 148591
2012-01-20 22:32:05 +00:00
Devang Patel
0638a44a24
Intel syntax: Parse ... PTR [-8]
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llvm-svn: 148570
2012-01-20 21:21:01 +00:00
Devang Patel
e836c95860
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
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llvm-svn: 148569
2012-01-20 21:14:06 +00:00
Jim Grosbach
4579f05f36
NEON use vmov.i32 to splat some f32 values into vectors.
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For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
llvm-svn: 148556
2012-01-20 18:09:51 +00:00
Devang Patel
b42cea31aa
Post process 'and', 'sub' instructions and select better encoding, if available.
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llvm-svn: 148489
2012-01-19 18:40:55 +00:00
Devang Patel
27ef211648
Intel syntax: There is no need to create unary expr for simple negative displacement.
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llvm-svn: 148486
2012-01-19 18:15:51 +00:00
Devang Patel
999eaa4b85
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
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llvm-svn: 148485
2012-01-19 17:53:25 +00:00
Jim Grosbach
48afa48c3e
Add testcase.
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llvm-svn: 148454
2012-01-19 01:36:59 +00:00
Jim Grosbach
b7ab9edb4e
Thumb2 alternate syntax for LDR(literal) and friends.
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Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
llvm-svn: 148432
2012-01-18 22:46:46 +00:00
Devang Patel
ee49d825b1
Process instructions after match to select alternative encoding which may be more desirable.
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llvm-svn: 148431
2012-01-18 22:42:29 +00:00
Jim Grosbach
a1e220fa82
Thumb2 relaxation for LDR(literal).
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If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.
rdar://10711829
llvm-svn: 148424
2012-01-18 21:54:16 +00:00
Jim Grosbach
e6d2a7a097
MC tweak symbol difference resolution for non-local symbols.
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When the non-local symbol in the expression is in the same fragment
as the second symbol, the assembler can still evaluate the expression
without needing a relocation.
For example, on ARM:
_foo:
ldr lr, (_foo - 4)
rdar://10348687
llvm-svn: 148341
2012-01-17 22:14:39 +00:00
Jim Grosbach
095e519996
Tidy up.
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llvm-svn: 148339
2012-01-17 22:03:42 +00:00
Devang Patel
e03a4f051f
Intel syntax: Fix parser match class to check memory operand size.
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llvm-svn: 148338
2012-01-17 21:48:03 +00:00
Devang Patel
4585b536ee
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
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llvm-svn: 148334
2012-01-17 21:25:10 +00:00
Devang Patel
388aa8feb0
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
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llvm-svn: 148321
2012-01-17 19:08:07 +00:00
Devang Patel
84d275a823
Intel syntax: Ignore mnemonic aliases.
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llvm-svn: 148316
2012-01-17 18:30:45 +00:00
Devang Patel
b1e07175c4
Intel syntax: Robustify memory operand parsing.
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llvm-svn: 148312
2012-01-17 18:00:18 +00:00