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Commit Graph

2658 Commits

Author SHA1 Message Date
Richard Sandiford
9867b44c59 [SystemZ] Add basic prefetch support
Just the instructions and intrinsics for now.

llvm-svn: 189100
2013-08-23 11:36:42 +00:00
Mihai Popa
dfdccf5f00 Fix ARM vcvt encoding when the number of fractional bits is zero.
The instruction to convert between floating point and fixed point representations
takes an immediate operand for the number of fractional bits of the fixed point
value. ARMARM specifies that when that number of bits is zero, the assembler
should encode floating point/integer conversion instructions. 

This patch adds the necessary instruction aliases to achieve this behaviour.

llvm-svn: 189009
2013-08-22 13:16:07 +00:00
Mihai Popa
721d6a74eb Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings.
To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV.

llvm-svn: 188901
2013-08-21 13:14:58 +00:00
Elena Demikhovsky
44bbb2b413 AVX-512: Added SHIFT instructions.
llvm-svn: 188899
2013-08-21 09:36:02 +00:00
Richard Sandiford
e3cc30d00b [SystemZ] Add FI[EDX]BRA
These are extensions of the existing FI[EDX]BR instructions, but use a spare
bit to suppress inexact conditions.

llvm-svn: 188894
2013-08-21 08:58:08 +00:00
Akira Hatanaka
297d5670ea [micromips] Print instruction alias "not" if the last operand of a nor is zero.
llvm-svn: 188851
2013-08-21 01:18:46 +00:00
Akira Hatanaka
ea8d1c863e [mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.

llvm-svn: 188824
2013-08-20 20:46:51 +00:00
Akira Hatanaka
5d76bb1499 [mips] Fix instruction definitions that were incorrectly marked as code-gen-only.
llvm-svn: 188690
2013-08-19 19:08:03 +00:00
Mihai Popa
db3c6274ef Thumb2 add immediate alias for SP
The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction.

All the patch does is adjust a register constraint on an instruction alias.

llvm-svn: 188676
2013-08-19 15:02:25 +00:00
Richard Sandiford
5e32ef0acd [SystemZ] Add negative integer absolute (load negative)
For now this matches the equivalent of (neg (abs ...)), which did hit a few
times in projects/test-suite.  We should probably also match cases where
absolute-like selects are used with reversed arguments.

llvm-svn: 188671
2013-08-19 12:56:58 +00:00
Richard Sandiford
aee0958460 [SystemZ] Add integer absolute (load positive)
llvm-svn: 188670
2013-08-19 12:48:54 +00:00
Hal Finkel
9591220c33 Add the PPC fcpsgn instruction
Modern PPC cores support a floating-point copysign instruction, and we can use
this to lower the FCOPYSIGN node (which is created from calls to the libm
copysign function). A couple of extra patterns are necessary because the
operand types of FCOPYSIGN need not agree.

llvm-svn: 188653
2013-08-19 05:01:02 +00:00
Mihai Popa
a9e072fd76 Add support for Thumb2 literal loads with negative zero offset
Thumb2 literal loads use an offset encoding which allows for 
negative zero. This fixes parsing and encoding so that #-0 
is correctly processed. The parser represents #-0 as INT32_MIN.

llvm-svn: 188549
2013-08-16 12:03:00 +00:00
Mihai Popa
cbf5f426e7 Fix Thumb2 aliasing complementary instructions taking modified immediates
There are many Thumb instructions which take 12-bit immediates encoded in a special
8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal
to transform an assembly instruction to be able to encode the immediate.

For example: AND and BIC are complementary instructions; one can switch the AND
to a BIC as long as the immediate is complemented. 

The intent is to switch one instruction into its complementary one when the immediate
cannot be encoded in the form requested in the original assembly and when the 
complementary immediate is encodable.

The patch addresses two issues:
1. definition of t2SOImmNot immediate - it has to check that the orignal value is
not encoded naturally
2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand 
rather than the ARM one.

llvm-svn: 188548
2013-08-16 11:55:44 +00:00
Richard Sandiford
06a13f49c8 [SystemZ] Use SRST to implement strlen and strnlen
It would also make sense to use it for memchr; I'm working on that now.

llvm-svn: 188547
2013-08-16 11:41:43 +00:00
Richard Sandiford
93a75a2a56 [SystemZ] Use MVST to implement strcpy and stpcpy
llvm-svn: 188546
2013-08-16 11:29:37 +00:00
Richard Sandiford
353c7bc810 [SystemZ] Use CLST to implement strcmp
llvm-svn: 188544
2013-08-16 11:21:54 +00:00
Vladimir Medic
5e1c2042a5 This patch implements wait instruction for mips. Examples are added in test files.
llvm-svn: 188537
2013-08-16 10:17:03 +00:00
Daniel Dunbar
a496d61c01 [tests] Cleanup initialization of test suffixes.
- Instead of setting the suffixes in a bunch of places, just set one master
   list in the top-level config. We now only modify the suffix list in a few
   suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).

 - Aside from removing the need for a bunch of lit.local.cfg files, this enables
   4 tests that were inadvertently being skipped (one in
   Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
   CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
   XFAILED).

 - This commit also fixes a bunch of config files to use config.root instead of
   older copy-pasted code.

llvm-svn: 188513
2013-08-16 00:37:11 +00:00
Mihai Popa
95a5647431 This fixes three issues related to Thumb literal loads:
1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020]
2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed
3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen
and the ASM parser, so this alias rule really does nothing

llvm-svn: 188466
2013-08-15 15:43:06 +00:00
Hao Liu
ad6d3a3db7 Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
llvm-svn: 188451
2013-08-15 08:26:11 +00:00
Tim Northover
2b579d35b4 Add test-case for hex floating-literals
Somehow I forgot to test one of the error conditions I'd added.

llvm-svn: 188372
2013-08-14 14:55:54 +00:00
Tim Northover
c40d142f19 Support C99 hexadecimal floating-point literals in assembly
It's useful to be able to write down floating-point numbers without having to
worry about what they'll be rounded to (as C99 discovered), this extends that
ability to the MC assembly parsers.

llvm-svn: 188370
2013-08-14 14:23:31 +00:00
Akira Hatanaka
6a7f10d027 [mips] Fix bug in parsing accumulator registers.
llvm-svn: 188344
2013-08-14 01:15:52 +00:00
Jack Carter
cb8856c2c6 [Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic

llvm-svn: 188312
2013-08-13 20:19:16 +00:00
Joey Gouly
c5221430a1 ARMv8: SWP and SWPB are obsoleted on ARMv8.
llvm-svn: 188288
2013-08-13 16:40:47 +00:00
Mihai Popa
f30d3c418d Fix signed overflow in when computing encodings for ADR instructions
llvm-svn: 188268
2013-08-13 14:02:13 +00:00
David Majnemer
eca1e24e80 [-cxx-abi microsoft] Stick zero initialized symbols into the .bss section for COFF
Summary:
We need to do two things:

- Initialize BSSSection in MCObjectFileInfo::InitCOFFMCObjectFileInfo
- Teach TargetLoweringObjectFileCOFF::SelectSectionForGlobal what to do
  with it

This fixes PR16861.

Reviewers: rnk

Reviewed By: rnk

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1361

llvm-svn: 188244
2013-08-13 01:23:53 +00:00
Kevin Enderby
41399cecad Fix a crash with X86 Mach-O and a subtraction expression where both symbols are
undefined and produce an error message instead as this is a non-relocatable
expression with X86 Mach-O.

rdar://8920876

llvm-svn: 188218
2013-08-12 22:45:44 +00:00
Vladimir Medic
34aca92bce This patch implements ei and di instructions for mips. Test cases are added.
llvm-svn: 188176
2013-08-12 13:07:23 +00:00
Tim Northover
67f2cc8ebf Fix FileCheck --check-prefix lines.
Various tests had sprung up over the years which had --check-prefix=ABC on the
RUN line, but "CHECK-ABC:" later on. This happened to work before, but was
strictly incorrect. FileCheck is getting stricter soon though.

Patch by Ron Ofir.

llvm-svn: 188173
2013-08-12 12:43:26 +00:00
Richard Sandiford
b10e77493f [SystemZ] Add a definition of the CLC instruction
llvm-svn: 188162
2013-08-12 10:17:33 +00:00
Richard Sandiford
aed77a47b8 [SystemZ] Add a definition of the IPM instruction
llvm-svn: 188161
2013-08-12 10:05:58 +00:00
Rafael Espindola
e297e56431 Check for $PWD in llvm::sys::current_path.
Some users (clang, libTooling) require this. After this patch we can remove
the calls to getenv("PWD") from clang.

llvm-svn: 188125
2013-08-10 00:50:57 +00:00
Mihai Popa
5aabbdc839 This fixes the Thumb2 CPS assembly syntax.
In Thumb1, only one variant is supported: CPS{effect} {flags}

Thumb2 supports three:
CPS{effect}.W {flags}
CPS{effect} {flags} {mode}
CPS {mode}

Canonically, .W should be used only when ambiguity is present between encodings of different width.
The wide suffix is still accepted for the latter two forms via aliases.

llvm-svn: 188071
2013-08-09 13:52:32 +00:00
Mihai Popa
b9642a712a Fix assembling of Thumb2 branch instructions.
The long encoding for Thumb2 unconditional branches is broken.
Additionally, there is no range checking for target operands; as such 
for instructions originating in assembly code, only short Thumb encodings
are generated, regardless of the bitsize needed for the offset.

Adding range checking is non trivial due to the representation of Thumb
branch instructions. There is no true difference between conditional and
unconditional branches in terms of operands and syntax - even unconditional
branches have a predicate which is expected to match that of the IT block
they are in. Yet, the encodings and the permitted size of the offset differ.

Due to this, for any mnemonic there are really 4 encodings to choose for.

The problem cannot be handled in the parser alone or by manipulating td files.
Because the parser builds first a set of match candidates and then checks them
one by one, whatever tablegen-only solution might be found will ultimately be
dependent of the parser's evaluation order. What's worse is that due to the fact
that all branches have the same syntax and the same kinds of operands, that 
order is governed by the lexicographical ordering of the names of operand 
classes...

To circumvent all this, any necessary disambiguation is added to the instruction
validation pass.

llvm-svn: 188067
2013-08-09 10:38:32 +00:00
Jack Carter
69e05b321a Mips ELF: MicroMips direct object Little endian support.
Test included.

Patch by Zoran Jovanovich

llvm-svn: 188024
2013-08-08 23:30:40 +00:00
David Majnemer
e90cbda29f Revert "coff also doesn't have a ReadOnlySection yet, (!)"
This reverts commit r77814.

We were sticking global constants in the .data section instead of in the
.rdata section when emitting for COFF.

This fixes PR16831.

llvm-svn: 187956
2013-08-08 01:50:52 +00:00
Eric Christopher
0cff1be367 Using the integrated assembler we'd fail to change section to the
.tbss section for zerofill thread locals. Make sure we do this
before emitting the zerofills.

Fixes PR15972.

llvm-svn: 187913
2013-08-07 21:13:06 +00:00
Richard Sandiford
5960348422 [SystemZ] Add floating-point load-and-test instructions
These instructions can also be used as comparisons with zero.

llvm-svn: 187882
2013-08-07 11:03:34 +00:00
Mihai Popa
89848e0624 This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)

llvm-svn: 187804
2013-08-06 16:07:46 +00:00
Mihai Popa
154c25a9c4 Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
llvm-svn: 187803
2013-08-06 15:52:36 +00:00
Richard Sandiford
92b3a35a0a [SystemZ] Add definitions for BRCT and BRCTG
llvm-svn: 187721
2013-08-05 11:07:38 +00:00
Richard Sandiford
18ee3fd7df [SystemZ] Add LOAD AND TEST instructions
Just the definitions and MC support.  The next patch uses them for codegen.

llvm-svn: 187719
2013-08-05 11:00:53 +00:00
Joey Gouly
9c798eabce [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.
llvm-svn: 187666
2013-08-02 19:18:12 +00:00
Elena Demikhovsky
3006e9bef0 EVEX and compressed displacement encoding for AVX512
llvm-svn: 187576
2013-08-01 13:34:06 +00:00
Vladimir Medic
3b5a138a7a Add tests for Mips DSP instructions.
llvm-svn: 187570
2013-08-01 09:35:25 +00:00
Tim Northover
dbac87d1fc AArch64: add initial NEON support
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

llvm-svn: 187567
2013-08-01 09:20:35 +00:00
Kevin Enderby
47a2c30349 Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match.  Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.

rdar://14214063

llvm-svn: 187530
2013-07-31 21:05:30 +00:00
Richard Sandiford
5869a6bb53 [SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.

llvm-svn: 187490
2013-07-31 11:17:35 +00:00