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184 Commits

Author SHA1 Message Date
Jack Carter
d66ed8368e This patch tackles the problem of parsing Mips 
register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic
llvm-svn: 172284
 2013-01-12 01:03:14 +00:00
Akira Hatanaka
9ed2d54e79 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.

llvm-svn: 170661
 2012-12-20 04:20:09 +00:00
Akira Hatanaka
9b0bb584d7 [mips] Delete all floating point instruction classes that are no longer used. 
No functionality change.

llvm-svn: 170084
 2012-12-13 02:05:02 +00:00
Akira Hatanaka
91fcd99fe7 [mips] Modify definitions of floating point comparison instructions. 
No functionality change.

llvm-svn: 170077
 2012-12-13 01:34:09 +00:00
Akira Hatanaka
a2c716142c [mips] Modify definitions of floating point branch instructions. 
No functionality change.

llvm-svn: 170076
 2012-12-13 01:32:36 +00:00
Akira Hatanaka
1adf30b9d9 [mips] Modify definitions of floating point indexed load and store instructions. 
No functionality change.

llvm-svn: 170075
 2012-12-13 01:30:49 +00:00
Akira Hatanaka
98db320b09 [mips] Modify definitions of floating point multiply-add/sub instructions. 
No functionality change.

llvm-svn: 170073
 2012-12-13 01:27:48 +00:00
Akira Hatanaka
c9ffc6e2aa [mips] Modify definitions of floating point load and store instructions. 
No functionality change.

llvm-svn: 170072
 2012-12-13 01:24:00 +00:00
Akira Hatanaka
8870233371 [mips] Modify definitions of move from/to coprocessor instructions. 
No functionality change.

llvm-svn: 170071
 2012-12-13 01:16:49 +00:00
Akira Hatanaka
ec241a272b [mips] Modify definitions of two register operand floating point instructions. 
No functionality change.

llvm-svn: 170069
 2012-12-13 01:14:07 +00:00
Akira Hatanaka
3e348c6459 [mips] Modify definitions of three register operand floating point instructions 
and separate encoding information from the rest.

llvm-svn: 170066
 2012-12-13 01:07:37 +00:00
Akira Hatanaka
5b3f83b790 [mips] Move classes that do not belong in MipsInstrFormats.td into 
MipsInstrFPU.td.
 

llvm-svn: 170061
 2012-12-13 00:49:23 +00:00
Akira Hatanaka
06623f41fb [mips] Set isCommutable flag in a more explicit way. 
llvm-svn: 170060
 2012-12-13 00:46:23 +00:00
Akira Hatanaka
17afb028f1 [mips] Remove fmt from the parameter list of classes FMADDSUB and FNMADDSUB. 
llvm-svn: 170057
 2012-12-13 00:38:59 +00:00
Akira Hatanaka
09dbe69401 [mips] Remove single-precision floating point instruction from multiclass 
FFR2P_M.
 

llvm-svn: 170055
 2012-12-13 00:35:54 +00:00
Akira Hatanaka
27204fd141 [mips] Remove single-precision floating point instructions from multiclasses 
FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
 

llvm-svn: 170053
 2012-12-13 00:29:29 +00:00
Akira Hatanaka
57161323ed [mips] Shorten predicate name. 
llvm-svn: 169579
 2012-12-07 03:06:09 +00:00
Akira Hatanaka
ee3532f807 [mips] Add predicate HasFPIdx for floating-point indexed load instruction 
support and use it in place of HasMips32r2Or64.

llvm-svn: 168089
 2012-11-15 21:17:13 +00:00
Akira Hatanaka
1bfa522bfe [mips] Set flag neverHasSideEffects flag on floating point conversion 
instructions.

llvm-svn: 167348
 2012-11-03 00:53:12 +00:00
Akira Hatanaka
03b00bdf4d Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and 
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.

No changes in functionality.

llvm-svn: 163960
 2012-09-15 01:52:08 +00:00
Akira Hatanaka
4e1b032521 Add stub methods for mips assembly matcher. 
Patch by Vladimir Medic.

llvm-svn: 162124
 2012-08-17 20:16:42 +00:00
Akira Hatanaka
e1beddb7e8 Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether 
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.

llvm-svn: 161071
 2012-07-31 19:13:07 +00:00
Akira Hatanaka
aab47c049b Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as 
single-precision load and store.

Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.

llvm-svn: 161063
 2012-07-31 18:16:49 +00:00
Akira Hatanaka
d1b2b96ed5 1. introduce MipsPat in place of Pat in order to exclude those from 
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.

llvm-svn: 158470
 2012-06-14 21:03:23 +00:00
Akira Hatanaka
2a600ff5f4 This patch adds a predicate to existing mips32 and mips64 so that those 
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
 2012-05-22 03:10:09 +00:00
Akira Hatanaka
ecb1cd1ce4 Add disassembler to MIPS. 
Patch by Vladimir Medic. 

llvm-svn: 154935
 2012-04-17 18:03:21 +00:00
Akira Hatanaka
48dbb62cb1 Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user, 
otherwise expand FNEG during legalization.

llvm-svn: 154546
 2012-04-11 22:59:08 +00:00
Akira Hatanaka
11a442d515 Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user. 
Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545
 2012-04-11 22:49:04 +00:00
Akira Hatanaka
cecb440c11 Revert r153924. There were buildbot failures. 
llvm-svn: 153925
 2012-04-03 02:51:09 +00:00
Akira Hatanaka
058b0cfb55 MIPS disassembler support. 
Patch by Vladimir Medic.

llvm-svn: 153924
 2012-04-03 02:20:58 +00:00
Akira Hatanaka
75b06f4a49 Fix bugs which were introduced when support for base+index floating point loads 
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843
 2012-03-01 22:12:30 +00:00
Jia Liu
bdcd314be3 remove blanks, and some code format 
llvm-svn: 151625
 2012-02-28 07:46:26 +00:00
Akira Hatanaka
0934449dd8 Add support for floating point base register + offset register addressing mode 
load and store instructions.

llvm-svn: 151611
 2012-02-28 02:55:02 +00:00
Akira Hatanaka
28521d25c9 Remove unnecessary template parameters. 
llvm-svn: 151540
 2012-02-27 19:17:53 +00:00
Akira Hatanaka
1e3ba02d8d Fix instruction predicates that were not set correctly. 
llvm-svn: 151538
 2012-02-27 19:09:08 +00:00
Akira Hatanaka
8fc9a35d3f Add definitions of floating point multiply add/sub and negative multiply 
add/sub instructions.

llvm-svn: 151415
 2012-02-25 00:21:52 +00:00
Akira Hatanaka
1593eafa1e Remove trailing whitespace. Add newline. 
llvm-svn: 150706
 2012-02-16 17:48:20 +00:00
Akira Hatanaka
12cdcf3bc6 Pattern for f32 to i64 conversion. 
llvm-svn: 148869
 2012-01-24 22:05:25 +00:00
Akira Hatanaka
36db890397 Various Mips64 floating point instruction patterns. 
llvm-svn: 144019
 2011-11-07 21:38:58 +00:00
Akira Hatanaka
cc6491001f Add definition of the base class for floating point comparison instructions 
and add Mips64's version too.

llvm-svn: 144018
 2011-11-07 21:37:33 +00:00
Akira Hatanaka
db8cbab444 Add definitions of 64-bit instructions which move data between integer and 
floating pointer registers.

llvm-svn: 144016
 2011-11-07 21:32:58 +00:00
Bruno Cardoso Lopes
edc2e30d42 Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
 2011-10-18 17:50:36 +00:00
Akira Hatanaka
e8cb50da87 Move class and instruction definitions for conditional moves to a seperate file. 
llvm-svn: 142220
 2011-10-17 18:43:19 +00:00
Akira Hatanaka
20808df5a0 Make changes necessary for supporting floating point load and store instructions 
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
 2011-10-11 01:12:52 +00:00
Akira Hatanaka
4a78bb776f Simplify definition of FP move instructions. 
llvm-svn: 141476
 2011-10-08 03:50:18 +00:00
Akira Hatanaka
7780dcc74e Define classes and multiclasses for FP binary instructions. 
llvm-svn: 141475
 2011-10-08 03:38:41 +00:00
Akira Hatanaka
9595e84a11 Define multiclasses for FP-to-FP instructions. 
llvm-svn: 141474
 2011-10-08 03:29:22 +00:00
Akira Hatanaka
e39c39db4a Define classes for FP unary instructions and multiclasses for FP-to-fixed point 
conversion instructions. 

llvm-svn: 141473
 2011-10-08 03:19:38 +00:00
Jakob Stoklund Olesen
6cb1647b24 Revert r140731, "Define classes for unary and binary FP instructions and use them to define" 
It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735
 2011-09-28 23:59:28 +00:00
Akira Hatanaka
be2c5236ec Define classes for unary and binary FP instructions and use them to define 
multiclasses.

llvm-svn: 140731
 2011-09-28 21:58:01 +00:00
Akira Hatanaka
0510b9d75b Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit. 
llvm-svn: 140705
 2011-09-28 18:11:19 +00:00
Akira Hatanaka
fa83d9ff16 Remove definitions of branch-on-FP-likely instructions. They are deprecated. 
llvm-svn: 140704
 2011-09-28 17:56:55 +00:00
Akira Hatanaka
ea4d87c3e8 Remove MipsFPRound. Mips1 is no longer supported. 
llvm-svn: 140661
 2011-09-27 23:55:37 +00:00
Akira Hatanaka
d44d75eccf Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside 
of the instruction definitions using Pat<>.

llvm-svn: 140644
 2011-09-27 22:01:01 +00:00
Akira Hatanaka
c83a0bb4b6 Make changes in instruction and pattern definitions so that tablegen does not 
complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354
 2011-09-22 23:31:54 +00:00
Akira Hatanaka
f65d050693 Drop support for Mips1 and Mips2. 
llvm-svn: 139405
 2011-09-09 20:45:50 +00:00
Akira Hatanaka
12df91513e Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711
 2011-08-16 03:51:51 +00:00
Akira Hatanaka
f56f544d80 Use tabs to separate opcode and operand strings. 
llvm-svn: 132718
 2011-06-07 18:16:51 +00:00
Akira Hatanaka
5b696387f7 Add pattern for double-to-integer conversion. Patch by Sasa Stankovic. 
llvm-svn: 131927
 2011-05-23 22:16:43 +00:00
Akira Hatanaka
a57b77b65f Fix setting of isCommutable flag. 
llvm-svn: 131233
 2011-05-12 17:42:08 +00:00
Eric Christopher
49409b8534 Fix td file comments for Mips. 
Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086
 2011-05-09 18:16:46 +00:00
Akira Hatanaka
74d45b54f1 Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. 
llvm-svn: 129612
 2011-04-15 21:51:11 +00:00
Akira Hatanaka
6f900185ed Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. 
llvm-svn: 129606
 2011-04-15 21:00:26 +00:00
Akira Hatanaka
025720d06f Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. 
llvm-svn: 129594
 2011-04-15 19:52:08 +00:00
Chris Lattner
0304b82f80 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Akira Hatanaka
b26c89ee68 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
llvm-svn: 128650
 2011-03-31 18:26:17 +00:00
Bruno Cardoso Lopes
5400401372 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Chris Lattner
01e8c46349 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Chris Lattner
a556264e06 fix emacs language spec's, patch by Edmund Grimley-Evans! 
llvm-svn: 111241
 2010-08-17 16:20:04 +00:00
Chris Lattner
99fafcf87e the FPCmp node returns an i32. 
llvm-svn: 99737
 2010-03-28 05:12:57 +00:00
Bruno Cardoso Lopes
a82b8ade4d Fix mov.d out register by using the FFR register class directly 
llvm-svn: 94914
 2010-01-30 18:29:19 +00:00
Bruno Cardoso Lopes
f87fd996e2 Disable ldc1/sdc1 instructions for mips1 targets. 
llvm-svn: 88887
 2009-11-16 04:35:29 +00:00
Bruno Cardoso Lopes
99e65b8707 A real solution for the first part of PR5445 
llvm-svn: 86895
 2009-11-11 23:09:33 +00:00
Bruno Cardoso Lopes
b662991460 Fix PR5445 
llvm-svn: 86651
 2009-11-10 02:35:13 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Bruno Cardoso Lopes
ddcbc31a99 Added support for fround, fextend and FP_TO_SINT 
llvm-svn: 72483
 2009-05-27 17:23:44 +00:00
Bruno Cardoso Lopes
fb1cd21342 Removed AFGR32 register class 
Handle odd registers allocation in FGR32.

llvm-svn: 67422
 2009-03-21 00:05:07 +00:00
Bruno Cardoso Lopes
463f306553 Handle i32->f32 bitconvert results. 
llvm-svn: 54315
 2008-08-04 06:44:31 +00:00
Bruno Cardoso Lopes
9181910033 Added pattern for floating point zero immediate (avoiding a constant pool 
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.

llvm-svn: 54229
 2008-07-30 19:00:31 +00:00
Bruno Cardoso Lopes
9d91fab260 Added floating point lowering for select. 
llvm-svn: 54167
 2008-07-29 19:05:28 +00:00
Bruno Cardoso Lopes
67af9a72f4 Added floating point lowering for setcc and brcond. 
Fixed COMM asm directive usage.
ConstantPool using custom FourByteConstantSection.

llvm-svn: 54139
 2008-07-28 19:11:24 +00:00
Bruno Cardoso Lopes
2bad4772e7 Fixe typos and 80 column size problems 
llvm-svn: 53272
 2008-07-09 04:45:36 +00:00
Bruno Cardoso Lopes
b0c10c758e fixed 32-bit fp_to_sint pattern 
llvm-svn: 53192
 2008-07-07 19:11:24 +00:00
Bruno Cardoso Lopes
d738f1e6c7 Several changes to Mips backend, experimental fp support being the most 
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.

llvm-svn: 53146
 2008-07-05 19:05:21 +00:00