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Commit Graph

132147 Commits

Author SHA1 Message Date
Craig Topper
29ae9d7e02 [AVX512] Rename vector extract instructions so 'mr' intead of 'rm' to reflect the fact that memory is the destination.
llvm-svn: 270332
2016-05-21 22:50:09 +00:00
Craig Topper
6bf6b5c2f4 [AVX512] Fix copy/paste mistake a I made in a comment.
llvm-svn: 270331
2016-05-21 22:50:04 +00:00
Chad Rosier
d150a4d1c1 Fix 80-column violation.
llvm-svn: 270329
2016-05-21 21:12:06 +00:00
Hal Finkel
be81a6f808 [LiveIntervalAnalysis] Don't dereference an end iterator in repairIntervalsInRange
This fixes a bug introduced in:

  r262115 - CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC

The iterator End here might == MBB->end(), and so we can't unconditionally
dereference it. This often goes unnoticed (I don't have a test case that always
crashes, and ASAN does not catch it either) because the function call arguments are
turned right back into iterators. MachineInstrBundleIterator's constructor,
however, does have an assert which might randomly fire.

llvm-svn: 270323
2016-05-21 16:03:50 +00:00
Michael Zuckerman
306643b672 [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics.
Differential Revision: http://reviews.llvm.org/D20438

llvm-svn: 270322
2016-05-21 14:44:18 +00:00
Michael Zuckerman
3d906b3ef7 [Clang][AVX512][intrinsics] Fix vscalef intrinsics.
Differential Revision: http://reviews.llvm.org/D20324

llvm-svn: 270321
2016-05-21 11:09:53 +00:00
George Rimar
8a63746f19 [llvm-readobj] - Teach readobj to recognize SHF_COMPRESSED flag.
Main problem here was that SHF_COMPRESSED has the same value with
XCORE_SHF_CP_SECTION, which was included as standart (common) flag.
As far I understand xCore is a family of controllers and it that
means it's constant should be processed separately,
only if e_machine == EM_XCORE, otherwise llvm-readobj would output
different constants twice for compressed section:

Flags [
..
SHF_COMPRESSED (0x800)
..
XCORE_SHF_CP_SECTION (0x800)
..
]

what probably does not make sence if you're not working with xcore file.

Differential revision: http://reviews.llvm.org/D20273

llvm-svn: 270320
2016-05-21 10:16:58 +00:00
Craig Topper
79cd5a6b41 [AVX512] Add patterns for VEXTRACT v16i16->v8i16 and v32i8->v16i8. Disable AVX2 versions of vector extract when AVX512VL is enabled.
llvm-svn: 270318
2016-05-21 07:08:56 +00:00
Craig Topper
f3e023e70e [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones.
llvm-svn: 270317
2016-05-21 06:07:18 +00:00
Craig Topper
30a8fe51db [AVX512] Disable AVX/AVX2 VBROADCASTSS/VBROADCASTSD patterns when AVX512VL is enabled.
llvm-svn: 270316
2016-05-21 05:47:25 +00:00
Craig Topper
12c223c367 [AVX512] Use update_llc_test_checks to update some tests so we can see all the instruction encodings and ensure everything is with EVEX.
llvm-svn: 270315
2016-05-21 05:46:58 +00:00
David Majnemer
cb9616636d [SimplifyCFG] Remove cleanuppads which are empty except for calls to lifetime.end
A cleanuppad is not cheap, they turn into many instructions and result
in additional spills and fills.  It is not worth keeping a cleanuppad
around if all it does is hold a lifetime.end instruction.

N.B.  We first try to merge the cleanuppad with another cleanuppad to
avoid dropping the lifetime and debug info markers.

llvm-svn: 270314
2016-05-21 05:12:32 +00:00
Craig Topper
e4f5166f4f [AVX512] Fix test cases I missed in r270311.
llvm-svn: 270313
2016-05-21 03:59:55 +00:00
Matt Arsenault
c4ee204f5c AMDGPU: Define priorities for register classes
Allocating larger register classes first should give better allocation
results (and more importantly for myself, make the lit tests more stable
with respect to scheduler changes).

Patch by Matthias Braun

llvm-svn: 270312
2016-05-21 03:55:07 +00:00
Craig Topper
2b54c30436 [AVX512] Disable AVX/AVX2 patterns for VPSADBW and VPMULUDQ when the AVX512VL/AVX512BWI equivalents are available.
llvm-svn: 270311
2016-05-21 03:52:32 +00:00
Craig Topper
8ca6c23ba5 [X86] Convert some SSE2/AVX2 intrinsics to ISD opcodes during lowering instead of pattern matching the intrinsics. This unifies handling with AVX512 and allows these intrinsics to select EVEX encoded instructions to increase available registers.
llvm-svn: 270310
2016-05-21 03:52:28 +00:00
Sanjoy Das
472411c719 [IRCE] Don't use an allocator for range checks; NFC
The InductiveRangeCheck struct is only five words long; so passing these
around value is fine.  The allocator makes the code look more complex
than it is.

llvm-svn: 270309
2016-05-21 02:52:13 +00:00
Sanjoy Das
2e4b716313 [IRCE] Don't pass IRBuilder<> where unnecessary; NFC
llvm-svn: 270308
2016-05-21 02:31:51 +00:00
Matt Arsenault
1eaf7c8b10 AMDGPU: Cleanup lowering actions
These are kind of a mess and hard to follow, particularly
for loads and stores. Fix various redundant, unnecessary
and dead settings.

llvm-svn: 270307
2016-05-21 02:27:49 +00:00
Sanjoy Das
9b7c91f0ad [GuardWidening] Fix incorrect use of remove_if
I had used `std::remove_if` under the assumption that it moves the
predicate matching elements to the end, but actaully the elements
remaining towards the end (after the iterator returned by
`std::remove_if`) are indeterminate.  Fix the bug (and make the code
more straightforward) by using a temporary SmallVector, and add a test
case demonstrating the issue.

llvm-svn: 270306
2016-05-21 02:24:44 +00:00
Matt Arsenault
44230570f6 AMDGPU: Fix high bits after division optimization
This is essentially doing a 24-bit signed division with FP.
We need to truncate to the N bit result.

llvm-svn: 270305
2016-05-21 01:53:33 +00:00
Quentin Colombet
9b5e08fa9b [RegBankSelect] Compute the repairing cost for copies.
Prior to this patch, we were using 1 for all the repairing costs.
Now, we use the information from the target to get this information.

llvm-svn: 270304
2016-05-21 01:43:25 +00:00
Quentin Colombet
a48386a2aa [RegisterBankInfo] Fix the initialization of the map VT to RegBank.
Prior to this patch we could have read uninitialized memory.

llvm-svn: 270303
2016-05-21 01:41:17 +00:00
Dylan McKay
d7d0f71629 [AVR] Add AVRMCAsmInfo
llvm-svn: 270302
2016-05-21 01:06:37 +00:00
Matt Arsenault
06895e862f AMDGPU: Fix verifier error when spilling SGPRs
The current SGPR spilling test does not stress this
because it is using s_buffer_load instructions to
increase SGPR pressure and spill, but their output
operands have the same SReg_32_XM0 constraint. This fixes
an error when the SReg_32 output from most instructions
is spilled.

llvm-svn: 270301
2016-05-21 00:53:42 +00:00
Matt Arsenault
4805dff2a5 AMDGPU: Fix relationship between SReg_32 and SReg_32_XM0
llvm-svn: 270300
2016-05-21 00:53:28 +00:00
Chris Bieneman
b1a11d081e Fix implicit type conversion. NFC.
llvm-svn: 270299
2016-05-21 00:36:47 +00:00
Dylan McKay
17a442f81e [AVR] Fix header files in MCTargetDesc
Everything now compiles successfully, but there are still undefined
references.

llvm-svn: 270298
2016-05-21 00:35:07 +00:00
Matt Arsenault
c34a7d2258 AMDGPU: Handle cbranch vccz/vccnz
llvm-svn: 270297
2016-05-21 00:29:40 +00:00
Matt Arsenault
5438a4669d AMDGPU: Implement ReverseBranchCondition
llvm-svn: 270296
2016-05-21 00:29:34 +00:00
Matt Arsenault
a197a65904 AMDGPU: Implement AnalyzeBranch
Original patch by Tom Stellard

llvm-svn: 270295
2016-05-21 00:29:27 +00:00
Dan Gohman
920c7d7490 [WebAssembly] Optimize away return instructions using fallthroughs.
This saves a small amount of code size, and is a first small step toward
passing values on the stack across block boundaries.

Differential Review: http://reviews.llvm.org/D20450

llvm-svn: 270294
2016-05-21 00:21:56 +00:00
Matt Arsenault
042c06f5a2 Fix constant folding of addrspacecast of null
This should not be making assumptions on the value of
the casted pointer.

llvm-svn: 270293
2016-05-21 00:14:04 +00:00
Dylan McKay
1126d23533 [AVR] Fix signuature of AVRTargetMachine constructor
llvm-svn: 270292
2016-05-20 23:39:04 +00:00
Matthias Braun
13037577f3 LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()
We now use LiveRangeCalc::extendToUses() instead of a specially designed
algorithm in constructMainRangeFromSubranges():
- The original motivation for constructMainRangeFromSubranges() were
  differences between the main liverange and subranges because of hidden
  dead definitions. This case however cannot happen anymore with the
  DetectDeadLaneMasks pass in place.
- It simplifies the code.
- This fixes a longstanding bug where we did not properly create new SSA
  values on merging control flow (the MachineVerifier missed most of
  these cases).
- Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and
  LiveRangeCalc to better match the implementation/available helper
  functions.

This re-applies r269016. The fixes from r270290 and r270259 should avoid
the machine verifier problems this time.

llvm-svn: 270291
2016-05-20 23:14:56 +00:00
Matthias Braun
327a7f0867 MachineVerifier: subregs so not require defs/valnos on every path
It is fine for subregister ranges to be undefined on some CFG paths as
we may have a "vregX:other_subreg<read-undef> =" def on that path. We
do not (and should not) have live segments for the subregister ranges.
The MachineVerifier should not complain about this.

This is a slight variant of http://llvm.org/PR27705

llvm-svn: 270290
2016-05-20 23:02:13 +00:00
Rui Ueyama
7c39439956 Fix struct member names and simplify. NFC.
llvm-svn: 270289
2016-05-20 22:59:05 +00:00
Tim Shen
a4d5b2aaf2 [PowerPC] Add a testcase for TCO on string rvo function
Differential Revision: http://reviews.llvm.org/D20311

llvm-svn: 270287
2016-05-20 22:42:01 +00:00
Chris Bieneman
c0ccb88987 [yaml2obj] [MachO] Fill Segment and Section data
This fills section data with 0xDEADBEEF and segment data not inside a section with 0xBAADDA7A. This results in yaml2obj generating a matching size object file. Any additional bytes in the file are zero'd.

This is a starting point for populating the remaining segment data, and provides a hex viewable file that you can easily see the missing data in.

llvm-svn: 270286
2016-05-20 22:31:50 +00:00
Sanjay Patel
df2ee08706 add test vector sdiv
llvm-svn: 270285
2016-05-20 22:08:40 +00:00
Sanjay Patel
38c18fba6e add test for vector shift
llvm-svn: 270284
2016-05-20 22:08:16 +00:00
Justin Bogner
20645f2085 SDAG: Implement Select instead of SelectImpl in PPCDAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
  the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

llvm-svn: 270283
2016-05-20 21:43:23 +00:00
Jacques Pienaar
4813cd5255 [lanai] Change reloc to use PIC_ by default and cleanup.
* Change reloc to PIC_;
* Cleanup (clang-format & modify test);

llvm-svn: 270282
2016-05-20 21:41:53 +00:00
Richard Smith
89657034a8 Switch from the linux-specific 'struct sigaltstack' to POSIX's 'stack_t'. This
is what I get for trusting my system's man pages I suppose.

llvm-svn: 270280
2016-05-20 21:38:15 +00:00
Richard Smith
74e8540951 Add a configure-time check for the existence of sigaltstack. It seems that some
systems provide a <signal.h> that doesn't declare it.

llvm-svn: 270278
2016-05-20 21:26:00 +00:00
Richard Smith
d86d870067 Reinstate r269992 (reverting r270267), but restricted to cases where glibc is
the C standard library implementation in use.

This works around a glibc bug in the backtrace() function where it fails to
produce a backtrace on x86_64 if libgcc / libunwind is statically linked.

llvm-svn: 270276
2016-05-20 21:18:12 +00:00
Richard Smith
1ae48ee8c8 Create a sigaltstack when we register our signal handlers. Otherwise we'd very
likely fail to produce a backtrace if we crash due to stack overflow.

llvm-svn: 270273
2016-05-20 21:07:41 +00:00
Michael Kuperstein
6f2a00d639 Revert r270268 due to unused variable warnings.
llvm-svn: 270272
2016-05-20 20:55:51 +00:00
Sanjay Patel
156965ba77 add tests for vector urem
llvm-svn: 270271
2016-05-20 20:55:17 +00:00
David Majnemer
08b442df36 Address post-review for r270246
This gets rid of some unnecessary SmallStrings in
X86TargetMachine::getSubtargetImpl.

No functionality change is intended.

llvm-svn: 270270
2016-05-20 20:41:24 +00:00