Dan Gohman
2a124430e9
Make this test x86-specific for now; targets that don't use
...
the automated CallingConv code to handle return values typically
don't support multiple return values.
llvm-svn: 48265
2008-03-12 00:25:14 +00:00
Dan Gohman
155ffdd955
Basic feature test for multiple return values in codegen.
...
llvm-svn: 48260
2008-03-11 23:53:16 +00:00
Anton Korobeynikov
d2fd135594
Testcase for PR2137
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llvm-svn: 48258
2008-03-11 22:43:42 +00:00
Anton Korobeynikov
efa9405b94
Update testcase for recent aliases change
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llvm-svn: 48250
2008-03-11 21:42:20 +00:00
Dan Gohman
f9f25bd41b
Add a test to ensure that all-ones vectors are materialized with pcmpeqd.
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llvm-svn: 48247
2008-03-11 21:37:00 +00:00
Dan Gohman
1fece90de9
Use the correct value for InSignBit.
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llvm-svn: 48245
2008-03-11 21:29:43 +00:00
Chris Lattner
fd2c24af72
Implement basic support for the 'f' register class constraint. This basically
...
works, but probably won't if you mix it with 't' or 'u' yet.
llvm-svn: 48243
2008-03-11 19:50:13 +00:00
Dale Johannesen
c03216ac3e
The feature this is testing did not work in the general case,
...
and has been removed.
llvm-svn: 48232
2008-03-11 17:48:26 +00:00
Evan Cheng
6a30fc4e94
Learn how to xfail a test.
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llvm-svn: 48219
2008-03-11 07:51:31 +00:00
Evan Cheng
af1c76846d
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
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llvm-svn: 48218
2008-03-11 07:19:34 +00:00
Evan Cheng
9ae65a13c3
XFAIL due to Dale's change.
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llvm-svn: 48216
2008-03-11 07:15:44 +00:00
Dan Gohman
85bfbe2293
Generalize ExpandIntToFP to handle the case where the operand is legal
...
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
llvm-svn: 48206
2008-03-11 01:59:03 +00:00
Scott Michel
599ff689d0
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
...
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
llvm-svn: 48197
2008-03-10 23:49:09 +00:00
Chris Lattner
f0684bfd16
Don't emit FP_REG_KILL into a block that just returns. Nothing
...
can be live out of the block anyway, so it isn't needed.
llvm-svn: 48192
2008-03-10 23:34:12 +00:00
Dan Gohman
67aed9bbb0
Implement more support for fp-to-i128 and i128-to-fp conversions.
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llvm-svn: 48189
2008-03-10 23:03:31 +00:00
Bill Wendling
8e3a4a45ce
Update llc flags for PPC register scavenger.
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llvm-svn: 48187
2008-03-10 22:59:08 +00:00
Dan Gohman
47137eba06
Fix mul expansion to check the correct number of bits for
...
zero extension when checking if an unsigned multiply is
safe.
llvm-svn: 48171
2008-03-10 20:42:19 +00:00
Dale Johannesen
62a0b6a79b
These tests don't work unless SSE2 is active.
...
Judging from the checking comments this is intentional,
so add the flag (makes them pass on non-x86 host).
llvm-svn: 48157
2008-03-10 17:33:57 +00:00
Dale Johannesen
c9ecee85c4
There is no "-mattr=+sse1" flag; fix test for non-x86 hosts.
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llvm-svn: 48156
2008-03-10 17:13:37 +00:00
Scott Michel
38f8a1043a
Integer comparison tests for CellSPU.
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llvm-svn: 48152
2008-03-10 16:58:52 +00:00
Evan Cheng
02b66c3a32
- Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where the source is defined; BLR is the live range which is defined by the copy.
...
If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
A = or A, B
...
B = A
...
C = A<kill>
...
= B
then do not add kills of A to the newly created B interval.
- Also fix some kill info update bug.
llvm-svn: 48141
2008-03-10 08:11:32 +00:00
Evan Cheng
3c0ddc999f
Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type (e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case.
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llvm-svn: 48136
2008-03-10 07:19:13 +00:00
Chris Lattner
95a37b6592
remove an execution test.
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llvm-svn: 48135
2008-03-10 06:53:14 +00:00
Evan Cheng
53424806b1
Fix RUN line.
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llvm-svn: 48116
2008-03-09 19:55:22 +00:00
Chris Lattner
b6bfedbcfd
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
...
an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
Chris Lattner
8d0203478f
Add ScheduleDAG support for copytoreg where the src/dst register are
...
in different register classes, e.g. copy of ST(0) to RFP*. This gets
some really trivial inline asm working that plops things on the top of
stack (PR879)
llvm-svn: 48105
2008-03-09 08:49:15 +00:00
Tanya Lattner
9aa573954c
Remove llvm-upgrade and update tests.
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llvm-svn: 48103
2008-03-09 08:16:40 +00:00
Chris Lattner
b9a4c86fbf
reduce this testcase more
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llvm-svn: 48092
2008-03-09 06:57:21 +00:00
Chris Lattner
b628208161
Finish implementing a readme entry: when inserting an i64 variable
...
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48090
2008-03-09 05:42:06 +00:00
Chris Lattner
17f68a3075
Implement a readme entry, compiling
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#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
llvm-svn: 48063
2008-03-09 01:05:04 +00:00
Chris Lattner
1b16dc4a6e
upgrade this test
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llvm-svn: 48062
2008-03-09 00:32:10 +00:00
Chris Lattner
24031c9426
make this test harder
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llvm-svn: 48061
2008-03-09 00:30:06 +00:00
Chris Lattner
7173d3bd70
Teach SD some vector identities, allowing us to compile vec_set-9 into:
...
_test3:
movd %rdi, %xmm1
#IMPLICIT_DEF %xmm0
punpcklqdq %xmm1, %xmm0
ret
instead of:
_test3:
#IMPLICIT_DEF %rax
movd %rax, %xmm0
movd %rdi, %xmm1
punpcklqdq %xmm1, %xmm0
ret
This is still not ideal. There is no reason to two xmm regs.
llvm-svn: 48058
2008-03-08 23:43:36 +00:00
Evan Cheng
dba1dfe962
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
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llvm-svn: 48042
2008-03-08 00:58:38 +00:00
Dan Gohman
afeac8050d
Add support for calls with i128 return values on ppc64.
...
llvm-svn: 48041
2008-03-08 00:19:12 +00:00
Dan Gohman
5bf464e1e6
Add support for lowering 128-bit shifts on ppc64.
...
llvm-svn: 48029
2008-03-07 20:36:53 +00:00
Evan Cheng
5f74d1a8dc
Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI.
...
llvm-svn: 48024
2008-03-07 20:12:54 +00:00
Chris Lattner
aa81dc7d21
mark frem as expand for all legal fp types on x86, regardless of whether
...
we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
2008-03-07 06:36:32 +00:00
Bill Wendling
f0615bf090
Add testcase.
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llvm-svn: 48005
2008-03-06 23:34:22 +00:00
Gabor Greif
92e00c1e50
some more spelling changes
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llvm-svn: 47996
2008-03-06 10:51:21 +00:00
Evan Cheng
9c77211639
Constant fold SIGN_EXTEND_INREG with ashr not lshr.
...
llvm-svn: 47992
2008-03-06 08:20:51 +00:00
Scott Michel
8dd2324903
Refine Cell's i64 constant generation code to cover more constants where the
...
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
llvm-svn: 47985
2008-03-06 04:02:54 +00:00
Scott Michel
3c19a3950c
- Expand tabs to spaces.
...
- select_bits.ll now fully functional now that PR1993 is closed. It was
previously broken by refactoring in SPUInstrInfo.td and using multiclasses.
- Same for eqv.ll
llvm-svn: 47972
2008-03-05 23:00:19 +00:00
Evan Cheng
8f5092bea8
Fix a coalescer bug wrt how dead copy interval is shortened.
...
llvm-svn: 47966
2008-03-05 22:09:42 +00:00
Chris Lattner
a9fcb187af
Generalize FP constant shrinking optimization to apply to any vt
...
except ppc long double. This allows us to shrink constant pool
entries for x86 long double constants, which in turn allows us to
use flds/fldl instead of fldt.
llvm-svn: 47938
2008-03-05 06:48:13 +00:00
Evan Cheng
e0b3c221ab
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
...
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
llvm-svn: 47931
2008-03-05 01:30:59 +00:00
Bill Wendling
cf70f2c2a0
Use -enable-ppc-regscavenger flag for these checks
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llvm-svn: 47916
2008-03-04 23:16:26 +00:00
Evan Cheng
14f556a6d7
Really fix the test.
...
llvm-svn: 47882
2008-03-04 08:01:56 +00:00
Evan Cheng
7a67175fcc
Fix broken test.
...
llvm-svn: 47881
2008-03-04 07:59:13 +00:00
Evan Cheng
3123d6ced3
Add PR1501 test case.
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llvm-svn: 47874
2008-03-04 00:47:45 +00:00