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Commit Graph

79040 Commits

Author SHA1 Message Date
Chris Lattner
c1d9c0a2a3 Now that PR11464 is fixed, reapply the patch to fix PR11464,
merging types by name when we can.  We still don't guarantee type name linkage
but we do it when obviously the right thing to do.  This makes LTO type names 
easier to read, for example.

llvm-svn: 146932
2011-12-20 00:12:26 +00:00
Chris Lattner
998998b3e7 fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all.
llvm-svn: 146929
2011-12-20 00:03:52 +00:00
Chris Lattner
151b0ec955 add a method to improve compatibility with SmallVector.
llvm-svn: 146928
2011-12-20 00:03:41 +00:00
Dan Gohman
7940e4e81d Add basic generic CodeGen support for half.
llvm-svn: 146927
2011-12-20 00:02:33 +00:00
Jim Grosbach
b1b83d2f58 ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

llvm-svn: 146925
2011-12-19 23:51:07 +00:00
Evan Cheng
9362ee62bc Move tests to FileCheck.
llvm-svn: 146923
2011-12-19 23:26:44 +00:00
Jim Grosbach
343f270350 ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658

llvm-svn: 146921
2011-12-19 23:06:24 +00:00
Evan Cheng
4c77fb5375 Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
 subeq  r0, r1, #1
 addne  r0, r1, #1                                                                                                                                                                                                     
into
 sub    r0, r1, #1
 addne  r0, r1, #1

For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
 op    r1, ...
 str   r1, [r10]        ; end-of-life of r1 as div result
 cmp   r0, #65
 movne r1, #44  ; raw dependency on previous r1
 moveq r1, #12

If movne is unpredicated, then
 op    r1, ...
 str   r1, [r10]
 cmp   r0, #65
 mov   r1, #44  ; r1 written unconditionally
 moveq r1, #12

Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.

This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.

rdar://8951196

llvm-svn: 146914
2011-12-19 22:01:30 +00:00
Eli Friedman
53dbd7d97f Add "using" to silence warnings.
llvm-svn: 146913
2011-12-19 21:53:12 +00:00
Akira Hatanaka
7ef923c1f0 Add a test case for r146900.
llvm-svn: 146901
2011-12-19 20:24:28 +00:00
Akira Hatanaka
e54da3bfa2 Add patterns for matching immediates whose lower 16-bit is cleared. These
patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900
2011-12-19 20:21:18 +00:00
Eli Friedman
602ab7a677 Attempt to fix PR11607 by shuffling around which class defines which methods.
llvm-svn: 146897
2011-12-19 20:06:03 +00:00
Akira Hatanaka
5ac6df52af Tidy up. Simplify logic. No functional change intended.
llvm-svn: 146896
2011-12-19 19:52:25 +00:00
Jim Grosbach
797a88284c ARM NEON two-operand aliases for VPADD.
rdar://10602276

llvm-svn: 146895
2011-12-19 19:51:03 +00:00
Akira Hatanaka
804863071f Remove definitions of double word shift plus 32 instructions. Assembler or
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893
2011-12-19 19:44:09 +00:00
Jim Grosbach
f9910809c5 ARM VFP pre-UAL mnemonic aliases for fmul[sd].
llvm-svn: 146892
2011-12-19 19:43:50 +00:00
Akira Hatanaka
ea1f905123 Remove unused predicate.
llvm-svn: 146889
2011-12-19 19:32:20 +00:00
Akira Hatanaka
b7ebcb2ded Remove the restriction on the first operand of the add node in SelectAddr.
This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)

llvm-svn: 146888
2011-12-19 19:28:37 +00:00
Jim Grosbach
6e9471925b ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
llvm-svn: 146887
2011-12-19 19:02:41 +00:00
Jim Grosbach
520db82971 ARM NEON implied destination aliases for VMAX/VMIN.
llvm-svn: 146885
2011-12-19 18:57:38 +00:00
Jim Grosbach
f4ca84a7ab ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884
2011-12-19 18:31:43 +00:00
Jim Grosbach
2a0ced60a5 Tidy up.
llvm-svn: 146882
2011-12-19 18:11:17 +00:00
Jakob Stoklund Olesen
7b1b08eb77 Remove a register class that can just as well be synthesized.
Add the new TableGen register class synthesizer feature to the release
notes.

llvm-svn: 146875
2011-12-19 16:53:40 +00:00
Jakob Stoklund Olesen
d409180ff3 Handle sub-register operands in recomputeRegClass().
Now that getMatchingSuperRegClass() returns accurate results, it can be
used to compute constraints imposed by instructions using a sub-register
of a virtual register.

This means we can recompute the register class of any virtual register
by combining the constraints from all its uses.

llvm-svn: 146874
2011-12-19 16:53:37 +00:00
Jakob Stoklund Olesen
0aa2f7755a Emit a getMatchingSuperRegClass() implementation for every target.
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

llvm-svn: 146873
2011-12-19 16:53:34 +00:00
Jakob Stoklund Olesen
78291d0bac Synthesize register classes for TRI::getMatchingSuperRegClass().
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results.  The function is
still not auto-generated, so it still returns inexact results.

This produces these new register classes:

ARM:
    QQPR_with_dsub_0_in_DPR_8
    QQQQPR_with_dsub_0_in_DPR_8
X86:
    GR64_with_sub_32bit_in_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
    GR64_with_sub_16bit_in_GR16_NOREX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
    GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
    GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
    GR64_with_sub_32bit_in_GR32_TC
    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
    GR64_with_sub_32bit_in_GR32_AD
    GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX

The other targets in the tree are not weird enough to be affected.

llvm-svn: 146872
2011-12-19 16:53:28 +00:00
Manuel Klimek
6e33b2fd7d Allow for benchmarking more than 4GB of memory
llvm-svn: 146864
2011-12-19 09:56:35 +00:00
Manuel Klimek
99a78498c5 Adds a flag to allow specifying the memory limitations of the JSON benchmark.
llvm-svn: 146863
2011-12-19 09:32:05 +00:00
Jakub Staszak
b62af984a1 - Use getExitingBlock instead of getExitingBlocks.
- Remove trailing spaces.

llvm-svn: 146854
2011-12-18 21:52:30 +00:00
Benjamin Kramer
942f1bd653 Another variadics tweak.
llvm-svn: 146852
2011-12-18 20:51:31 +00:00
Joerg Sonnenberger
8cf8d64d19 Allow inlining of functions with returns_twice calls, if they have the
attribute themselve.

llvm-svn: 146851
2011-12-18 20:35:43 +00:00
Benjamin Kramer
e16533eded Use the fancy new VariadicFunction template instead of a plain variadic function.
Some compilers were complaining about passing StringRef to it.

llvm-svn: 146850
2011-12-18 19:59:20 +00:00
Dylan Noblesmith
f9c9d1b4d0 capitalize project name, reference bugzilla
And fix the double-[]. It was including the [] as part of
the project name somehow, resulting in PACKAGE_TARNAME "-llvm-"
and a strange docdir default:

./configure --help | grep docdir
  --docdir=DIR           documentation root [DATAROOTDIR/doc/-llvm-]

llvm-svn: 146849
2011-12-18 18:50:16 +00:00
Benjamin Kramer
dd2a4b1e4f Hexagon: Remove unused variables.
llvm-svn: 146846
2011-12-18 12:00:09 +00:00
Chad Rosier
b870a13cd8 Revert 146728 as it's causing failures on some of the external bots as well as
internal nightly testers.  Original commit message:

By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large
app.

llvm-svn: 146838
2011-12-17 22:19:53 +00:00
Kevin Enderby
42fffe915a Revert r146822 at Pete Cooper's request as it broke clang self hosting.
Hope I did this correctly :)

llvm-svn: 146834
2011-12-17 19:48:52 +00:00
Craig Topper
9696094d07 Remove an unused X86ISD node type.
llvm-svn: 146833
2011-12-17 19:16:44 +00:00
Benjamin Kramer
65c1236c63 X86: Factor the bswap asm matching to be slightly less horrible to read.
llvm-svn: 146831
2011-12-17 14:36:05 +00:00
Chandler Carruth
c8e6351626 As Doug pointed out (and I really should know), it is perfectly easy to
make VariadicFunction actually be trivial. Do so, and also make it look
more like your standard trivial functor by making it a struct with no
access specifiers. The unit test is updated to initialize its functors
properly.

llvm-svn: 146827
2011-12-17 10:20:15 +00:00
Pete Cooper
0ec73f6e98 SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands.
For example, 

if (a == b) {
    if (a > b) // this is false
    
Fixes some of the issues on <rdar://problem/10554090>

llvm-svn: 146822
2011-12-17 06:32:38 +00:00
Manuel Klimek
09f4d148b8 Deleting the json-bench-test until I understand why it is flaky.
llvm-svn: 146821
2011-12-17 06:29:32 +00:00
Evan Cheng
23574ec02a Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
llvm-svn: 146805
2011-12-17 01:25:34 +00:00
Pete Cooper
6627aaa416 Refactor code used in InstCombine::FoldAndOfICmps to new file.
This will be used by SimplifyCfg in a later commit.

llvm-svn: 146803
2011-12-17 01:20:32 +00:00
Rafael Espindola
549d0683b1 Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
asm parsing and testcase.

llvm-svn: 146801
2011-12-17 01:14:52 +00:00
Lang Hames
e32ef23ba8 Make sure that the lower bits on the VSELECT condition are properly set.
llvm-svn: 146800
2011-12-17 01:08:46 +00:00
Jakob Stoklund Olesen
7d7ba18ad7 Preserve more memory operands in ARMExpandPseudo.
I don't think this affects anything but verbose assembly.

llvm-svn: 146787
2011-12-17 00:07:02 +00:00
Dan Gohman
9c8c9a8f62 The powers that be have decided that LLVM IR should now support 16-bit
"half precision" floating-point with a first-class type.

This patch adds basic IR support (but not codegen support).

llvm-svn: 146786
2011-12-17 00:04:22 +00:00
Eric Christopher
38b0b94ef2 When recursing for the original size of a type, stop if we are at a
pointer or a reference type - we actually just want the size of the
pointer then for that.

Fixes rdar://10335756

llvm-svn: 146785
2011-12-16 23:42:45 +00:00
Eric Christopher
b9b1a7d40e Resolve part of a fixme and add a new one.
llvm-svn: 146784
2011-12-16 23:42:42 +00:00
Eric Christopher
bceac3c150 Add a fixme here.
llvm-svn: 146783
2011-12-16 23:42:38 +00:00