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213 Commits

Author SHA1 Message Date
Tom Stellard
33e7a52e1c R600: Use correct CF_END instruction on Northern Island GPUs 
llvm-svn: 180735
 2013-04-29 22:23:58 +00:00
Tom Stellard
a22d2b47f3 R600: Fix encoding of CF_END_{EG, R600} instructions 
The EOP bit was not being encoded.

llvm-svn: 180734
 2013-04-29 22:23:54 +00:00
Tom Stellard
de2ad0a8f1 R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 
We need to intialize this to something and since clang does not set
the shader type attribute and clang is used only for compute shaders,
initializing it to COMPUTE seems like the best choice.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 180620
 2013-04-26 18:32:24 +00:00
Tom Stellard
222f7ab2fb R600: Initialize BooleanVectorContents 
Fixes test/CodeGen/R600/setcc.ll

llvm-svn: 180231
 2013-04-24 23:56:18 +00:00
Tom Stellard
48d161332e R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

llvm-svn: 180230
 2013-04-24 23:56:14 +00:00
Vincent Lejeune
3666f07489 R600: Use .AMDGPU.config section to emit stacksize 
llvm-svn: 180124
 2013-04-23 17:34:12 +00:00
Vincent Lejeune
e5ba5f1b14 R600: Add CF_END 
llvm-svn: 180123
 2013-04-23 17:34:00 +00:00
Matt Arsenault
b7287bba9b Remove unused DwarfSectionOffsetDirective string 
The value isn't actually used, and setting it emits a COFF specific
directive.

llvm-svn: 180064
 2013-04-22 22:49:11 +00:00
Michael Liao
3b258b6b24 ArrayRefize getMachineNode(). No functionality change. 
llvm-svn: 179901
 2013-04-19 22:22:57 +00:00
Tom Stellard
017c53ebbd R600: Add pattern for the BFI_INT instruction 
llvm-svn: 179830
 2013-04-19 02:11:06 +00:00
Tom Stellard
db47653487 R600/SI: Use InstFlag for VOP3 modifier operands 
InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179829
 2013-04-19 02:11:00 +00:00
Vincent Lejeune
cd0483fb18 R600: Make Export Instruction not duplicable 
llvm-svn: 179686
 2013-04-17 15:17:39 +00:00
Vincent Lejeune
a1a9b1752d R600: Export is emitted as a CF_NATIVE inst 
llvm-svn: 179685
 2013-04-17 15:17:32 +00:00
Vincent Lejeune
966453087f R600: Emit used GPRs count 
llvm-svn: 179684
 2013-04-17 15:17:25 +00:00
Tom Stellard
bd67f8cd81 R600/SI: Emit config values in register value pairs. 
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546
 2013-04-15 17:51:35 +00:00
Tom Stellard
a44e2e18a1 R600/SI: Emit configuration value in the .AMDGPU.config ELF section 
llvm-svn: 179545
 2013-04-15 17:51:30 +00:00
Tom Stellard
cb4468b00a R600: Emit ELF formatted code rather than raw ISA. 
llvm-svn: 179544
 2013-04-15 17:51:21 +00:00
NAKAMURA Takumi
c9309ae42b R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable] 
llvm-svn: 179263
 2013-04-11 04:16:27 +00:00
NAKAMURA Takumi
1837d9ec3e Whitespace. 
llvm-svn: 179262
 2013-04-11 04:16:22 +00:00
Michel Danzer
c1562afdde R600/SI: Add pattern for AMDGPUurecip 
21 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 179186
 2013-04-10 17:17:56 +00:00
Vincent Lejeune
daa1e69206 R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addr 
llvm-svn: 179174
 2013-04-10 13:29:20 +00:00
Christian Konig
f40f671bab R600/SI: dynamical figure out the reg class of MIMG 
Depending on the number of bits set in the writemask.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179166
 2013-04-10 08:39:16 +00:00
Christian Konig
76cd1a76c2 R600/SI: adjust writemask to only the used components 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179165
 2013-04-10 08:39:08 +00:00
Christian Konig
ffddac18a4 R600/SI: remove image sample writemask 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179164
 2013-04-10 08:39:01 +00:00
Vincent Lejeune
cbdacdc057 R600: Control Flow support for pre EG gen 
llvm-svn: 179020
 2013-04-08 13:05:49 +00:00
Tom Stellard
8ad4f7c25b R600/SI: Add support for buffer stores v2 
v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178931
 2013-04-05 23:31:51 +00:00
Tom Stellard
379d612a66 R600/SI: Use same names for corresponding MUBUF operands and encoding fields 
The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178930
 2013-04-05 23:31:44 +00:00
Tom Stellard
7dd3fda85d R600: Add RV670 processor 
This is an R600 GPU with double support.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178929
 2013-04-05 23:31:40 +00:00
Tom Stellard
917d7412f1 R600/SI: Add processor types for each SI variant 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178928
 2013-04-05 23:31:35 +00:00
Tom Stellard
17fba38a4b R600/SI: Avoid generating S_MOVs with 64-bit immediates v2 
SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate.  Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.

v2:
  - Clean up logic

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178927
 2013-04-05 23:31:20 +00:00
Vincent Lejeune
3a22d07044 R600: Use a mask for offsets when encoding instructions 
llvm-svn: 178763
 2013-04-04 14:00:09 +00:00
Vincent Lejeune
d5f0b3821e R600: Fix wrong address when substituting ENDIF 
llvm-svn: 178762
 2013-04-04 14:00:03 +00:00
Vincent Lejeune
a680946842 R600: Take export into account when computing cf address 
llvm-svn: 178761
 2013-04-04 13:59:59 +00:00
Vincent Lejeune
6a4ef74f44 R600: Fix last ALU of a clause being emitted in a separate clause 
llvm-svn: 178675
 2013-04-03 18:24:47 +00:00
Vincent Lejeune
9bc67cfa08 R600: Factorize maximum alu per clause in a single location 
llvm-svn: 178667
 2013-04-03 16:49:34 +00:00
Vincent Lejeune
bab4692335 R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizer 
llvm-svn: 178665
 2013-04-03 16:24:09 +00:00
Vincent Lejeune
6b257b347d R600: Consider KILLGT as an ALU instruction 
Mesa does not override llvm behavior wrt KILLGT anymore so llvm
has to handle KILLGT on its own.

llvm-svn: 178664
 2013-04-03 16:24:04 +00:00
NAKAMURA Takumi
9ce5fbdaab Target/R600: Fix CMake build to add missing files. 
llvm-svn: 178508
 2013-04-01 22:05:58 +00:00
Vincent Lejeune
dc0e12bd5b R600: Add support for native control flow 
llvm-svn: 178505
 2013-04-01 21:48:05 +00:00
Vincent Lejeune
8b37b0c9c6 R600/SI: Share code recording ShaderTypeAttribute between generations 
llvm-svn: 178504
 2013-04-01 21:47:53 +00:00
Vincent Lejeune
11918406b3 R600: Emit CF_ALU and use true kcache register. 
llvm-svn: 178503
 2013-04-01 21:47:42 +00:00
Vincent Lejeune
30dc10604e R600: Emit native instructions for tex 
llvm-svn: 178452
 2013-03-31 19:33:04 +00:00
Eric Christopher
43672e076b These two are default in the constructor for MCAsmInfo. 
llvm-svn: 178293
 2013-03-28 21:37:18 +00:00
Christian Konig
510c335233 R600/SI: add SETO/SETUO patterns 
6 more piglit tests.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178145
 2013-03-27 15:27:31 +00:00
Christian Konig
fb305cbcea R600/SI: add cummuting of rev instructions 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178127
 2013-03-27 09:12:59 +00:00
Christian Konig
231ee3f1ae R600/SI: add mulhu/mulhs patterns 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178126
 2013-03-27 09:12:51 +00:00
Christian Konig
c90c1dabd1 R600/SI: add srl/sha patterns for SI 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178125
 2013-03-27 09:12:44 +00:00
NAKAMURA Takumi
f508219ce8 R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. [-Wunused-private-field] 
llvm-svn: 178065
 2013-03-26 19:42:48 +00:00
Christian Konig
3548ce0f01 R600/SI: improve post ISel folding 
Not only fold immediates, but avoid unnecessary copies as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178024
 2013-03-26 14:04:17 +00:00
Christian Konig
d8fe8c3e97 R600/SI: improve vector interpolation 
Prevent loading M0 multiple times.

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178023
 2013-03-26 14:04:12 +00:00