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Commit Graph

208661 Commits

Author SHA1 Message Date
Matt Arsenault
3419b798ef AMDGPU: Add spilled CSR SGPRs to entry block live ins 2020-12-22 21:55:59 -05:00
ShihPo Hung
a268fdb29f [RISCV] Add intrinsics for vf[n]macc/vf[n]msac/vf[n]madd/vf[n]msub instructions
This patch defines vfmadd/vfnmacc, vfmsac/vfnmsac, vfmadd/vfnmadd,
and vfmsub/vfnmsub lower to V instructions.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93691
2020-12-22 18:34:00 -08:00
ShihPo Hung
ec91727e53 [RISCV] Add intrinsics for vwmacc[u|su|us] instructions
This patch defines vwmacc[u|su|us] intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93675
2020-12-22 18:17:39 -08:00
ShihPo Hung
819a1811bd [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction
This patch adds intrinsics for vslide1up, vslide1down, vfslide1up, vfslide1down.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93608
2020-12-22 18:14:22 -08:00
Matt Arsenault
a33259aebe AMDGPU: Fix assert when checking for implicit operand legality 2020-12-22 20:56:24 -05:00
Matt Arsenault
43e94d4c6a VirtRegMap: Use Register 2020-12-22 20:56:14 -05:00
Arthur O'Dwyer
bf9fb2bea1 Replace T(x) with reinterpret_cast<T>(x) everywhere it means reinterpret_cast. NFC.
Differential Revision: https://reviews.llvm.org/D76572
2020-12-22 19:54:29 -05:00
Stanislav Mekhanoshin
09ef5f7bec [AMDGPU][GlobalISel] GlobalISel for flat scratch
It does not seem to fold offsets but this is not specific
to the flat scratch as getPtrBaseWithConstantOffset() does
not return the split for these tests unlike its SDag
counterpart.

Differential Revision: https://reviews.llvm.org/D93670
2020-12-22 16:33:06 -08:00
Stanislav Mekhanoshin
b2c1643118 [AMDGPU] Support unaligned flat scratch in TLI
Adjust SITargetLowering::allowsMisalignedMemoryAccessesImpl for
unaligned flat scratch support. Mostly needed for global isel.

Differential Revision: https://reviews.llvm.org/D93669
2020-12-22 16:12:31 -08:00
Thomas Lively
92eadd3cde [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats
These instructions previously used prefixes like v8x16 to signify that they were
agnostic between float and int interpretations. We renamed these instructions to
remove this form of prefix in https://github.com/WebAssembly/simd/issues/297 and
https://github.com/WebAssembly/simd/issues/316 and this commit brings the names
in LLVM up to date.

Differential Revision: https://reviews.llvm.org/D93722
2020-12-22 14:29:06 -08:00
Sanjay Patel
4ddc126029 [SLP] add reduction tests for maxnum/minnum intrinsics; NFC 2020-12-22 16:05:39 -05:00
Sanjay Patel
39bfb797e5 [SLP] use operand index abstraction for number of operands
I think this is NFC currently, but the bug would be exposed
when we allow binary intrinsics (maxnum, etc) as candidates
for reductions.

The code in matchAssociativeReduction() is using
OperationData::getNumberOfOperands() when comparing whether
the "EdgeToVisit" iterator is in-bounds, so this code must
use the same (potentially offset) operand value to set
the "EdgeToVisit".
2020-12-22 16:05:39 -05:00
Craig Topper
ab5054f7c8 [RISCV] Remove unneeded !eq comparing a single bit value to 0/1 in RISCVInstrInfoVPseudos.td. NFC
Instead we can either use the bit directly. If it was checking for
0 we need to swap the operands or use !not.
2020-12-22 11:57:16 -08:00
Arnold Schwaighofer
213a4b317b Add a llvm.coro.end.async intrinsic
The llvm.coro.end.async intrinsic allows to specify a function that is
to be called as the last action before returning. This function will be
inlined after coroutine splitting.

This function can contain a 'musttail' call to allow for guaranteed tail
calling as the last action.

Differential Revision: https://reviews.llvm.org/D93568
2020-12-22 10:52:28 -08:00
Stanislav Mekhanoshin
90da9cd31d [AMDGPU] Folding of FI operand with flat scratch
Differential Revision: https://reviews.llvm.org/D93501
2020-12-22 10:48:04 -08:00
sameeran joshi
1f7bfce5b3 Revert "[Flang][openmp][5.0] Add task_reduction clause."
This reverts commit 9a7895dc20852b662a66976d06871ec2a0b968c8.
Reverting due to missing Co-author attribution.

https://reviews.llvm.org/D93105
2020-12-22 23:53:51 +05:30
Nathan James
201e2329a7 [ADT] Fix some tests after 5d10b8ad
Some bots were failing due to signed/unsigned comparison.
2020-12-22 18:06:19 +00:00
Florian Hahn
b4471f9735 [LoopDeletion] Add test case where outer loop needs to be deleted.
In the test case @test1, the inner loop cannot be removed, because it
has a live-out value. But the outer loop is a no-op and can be removed.
2020-12-22 17:49:20 +00:00
Philip Reames
9dce9d4c76 [tests] precommit a test mentioned in review for D93317 2020-12-22 09:47:19 -08:00
Nathan James
b6e73d2ad1 [ADT] Add resize_for_overwrite method to SmallVector.
Analagous to the std::make_(unqiue|shared)_for_overwrite added in c++20.
If T is POD, and the container gets larger, any new values added wont be initialized.
This is useful when using SmallVector as a buffer where its planned to overwrite any potential new values added.
If T is not POD, `new (Storage) T` functions identically to `new (Storage) T()` so this will function identically to `resize(size_type)`.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D93532
2020-12-22 17:18:59 +00:00
Paul Walker
70073e607b Fix some misnamed variables in sve-fixed-length-int-minmax.ll. 2020-12-22 17:11:23 +00:00
Kamau Bridgeman
86aa55c858 [PowerPC][Power10] Exploit store rightmost vector element instructions
Using the store rightmost vector element instructions to do vector
element extraction and store. The rightmost vector element on little
endian is the zeroth vector element, with these patterns that element
can be extracted and stored in one instruction for all vector types.

Differential Revision: https://reviews.llvm.org/D89195
2020-12-22 12:06:43 -05:00
sameeran joshi
d525c0db00 [Flang][openmp][5.0] Add task_reduction clause.
See OMP-5.0 2.19.5.5 task_reduction Clause.
To add a positive test case we need `taskgroup` directive which is not added hence skipping the test.
This is a dependency for `taskgroup` construct.

Reviewed By: clementval

Differential Revision: https://reviews.llvm.org/D93105
2020-12-22 22:34:38 +05:30
Paul Walker
1499ac0fc7 [SVE] Lower vector BITREVERSE and BSWAP operations.
These operations are lowered to RBIT and REVB instructions
respectively.  In the case of fixed-length support using SVE we
also lower BITREVERSE operating on NEON sized vectors as this
results in fewer instructions.

Differential Revision: https://reviews.llvm.org/D93606
2020-12-22 16:49:50 +00:00
Nandor Licker
b6ede64cc1 [RISCV] Basic jump table lowering
This patch enables jump table lowering in the RISC-V backend.

In addition to the test case included, the new lowering was
tested by compiling the OCaml runtime and running it under qemu.

Differential Revision: https://reviews.llvm.org/D92097
2020-12-22 15:05:54 +00:00
clementval
503c7c65fe [openacc][openmp][NFC] Fix typo in comments 2020-12-22 09:59:50 -05:00
Florian Hahn
4cdccd0b93 [LV] Use ScalarEvolution::getURemExpr to reduce duplication.
ScalarEvolution should be able to handle both constant and variable trip
counts using getURemExpr, so we do not have to handle them separately.

This is a small simplification of a56280094e08.

Reviewed By: gilr

Differential Revision: https://reviews.llvm.org/D93677
2020-12-22 14:48:42 +00:00
Paul C. Anagnostopoulos
e6292b9b96 [MCInstrDesc] [TableGen] Reduce size of MCOperandInfo instances.
Differential Revision: https://reviews.llvm.org/D93326
2020-12-22 09:44:30 -05:00
Jan Svoboda
f04bf685e6 [clang][cli] Implement getAllArgValues marshalling
This infrastructure can be used ~30 more command line options.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D93631
2020-12-22 14:11:16 +01:00
Sjoerd Meijer
e92d6b8dd8 [AArch64] Add a test for MachineLICM SinkIntoLoop. NFC. 2020-12-22 12:22:24 +00:00
Nico Weber
101d5213c5 Revert "-fstack-clash-protection: Return an actual error when used on unsupported OS"
This reverts commit 4d59c8fdb955ea0d668b854f467e12bce05a8857.
Breaks tens of thousands of tests, and had pending review comments, see
comments on https://reviews.llvm.org/D92245 (and e.g.
http://lab.llvm.org:8011/#/builders/109/builds/5236 for failures).
2020-12-22 06:51:19 -05:00
Nemanja Ivanovic
437b6055f0 [PowerPC] Restore stack ptr from base ptr when available
On subtargets that have a red zone, we will copy the stack pointer to the base
pointer in the prologue prior to updating the stack pointer. There are no other
updates to the base pointer after that. This suggests that we should be able to
restore the stack pointer from the base pointer rather than loading it from the
back chain or adding the frame size back to either the stack pointer or the
frame pointer.
This came about because functions that call setjmp need to restore the SP from
the FP because the back chain might have been clobbered
(see https://reviews.llvm.org/D92906). However, if the stack is realigned, the
restored SP might be incorrect (which is what caused the failures in the two
ASan test cases).

This patch was tested quite extensivelly both with sanitizer runtimes and
general code.

Differential revision: https://reviews.llvm.org/D93327
2020-12-22 05:44:03 -06:00
Nico Weber
88d23da9ea [gn build] (manually) port b8c37153d5393 2020-12-22 06:35:40 -05:00
David Spickett
fe844f277e [llvm][Arm/AArch64] Format extension flags in CPU test failures
Previously you just two hex numbers you had to decode manually.
This change adds a predicate formatter for extension flags
to produce failure messages like:
```
[ RUN      ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2
<...>llvm/unittests/Support/TargetParserTest.cpp:862:
Failure
Expected extension flags: +fp-armv8, +crc, +crypto (0xe)
     Got extension flags: +fp-armv8, +neon, +crc, +crypto (0x1e)
[  FAILED  ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2,
where GetParam() = "cortex-a34", "armv8-a", <...>
```

From there you can take the feature name and map it back
to the enum in ARM/AArch64TargetParser.def.
(which isn't perfect but you've probably got both files
open if you're editing these tests)

Note that AEK_NONE is not meant to be user facing in the compiler
but here it is part of the tests. So failures may show an
extension "none" where the normal target parser wouldn't.

The formatter is implemented as a template on ARM::ISAKind
because the predicate formatters assume all parameters are used
for comparison.
(e.g. PRED_FORMAT3 is for comparing 3 values, not having 3
arguments in general)

Reviewed By: MarkMurrayARM

Differential Revision: https://reviews.llvm.org/D93448
2020-12-22 11:13:36 +00:00
Sylvestre Ledru
3ce38f4632 -fstack-clash-protection: Return an actual error when used on unsupported OS
$ clang-12: error: -fstack-clash-protection is not supported on Windows or Mac OS X

Differential Revision: https://reviews.llvm.org/D92245
2020-12-22 12:06:08 +01:00
Siddhesh Poyarekar
f256168c20 Fold comparison of __builtin_object_size expression with -1 for non-const size
When __builtin_dynamic_object_size returns a non-constant expression, it cannot
be -1 since that is an invalid return value for object size. However since
passes running after the substitution don't know this, they are unable to
optimize away the comparison and hence the comparison and branch stays in there.
This change generates an appropriate call to llvm.assume to help the optimizer
folding the test.

glibc is considering adopting __builtin_dynamic_object_size for additional
protection[1] and this change will help reduce branching overhead in fortified
implementations of all of the functions that don't have the __builtin___*_chk
type builtins, e.g. __ppoll_chk.

Also remove the test limit-max-iterations.ll because it was deemed unnecessary
during review.

[1] https://sourceware.org/pipermail/libc-alpha/2020-November/120191.html

Differential Revision: https://reviews.llvm.org/D93015
2020-12-22 10:56:31 +01:00
Florian Hahn
f84e692f2b [VPlan] Make VPInstruction a VPDef
This patch turns updates VPInstruction to manage the value it defines
using VPDef. The VPValue is used  during VPlan construction and
codegeneration instead of the plain IR reference where possible.

Reviewed By: gilr

Differential Revision: https://reviews.llvm.org/D90565
2020-12-22 09:53:47 +00:00
Sjoerd Meijer
cf31f6d3c6 [MachineLICM] Add llvm debug messages to SinkIntoLoop. NFC.
I am investigating sinking instructions back into the loop under high
register pressure. This is just a first NFC step to add some debug
messages that allows tracing of the decision making.
2020-12-22 09:19:43 +00:00
Pavel Labath
968624617c [DebugInfo] Don't use DW_OP_implicit_value for fragments
Currently using DW_OP_implicit_value in fragments produces invalid DWARF
expressions. (Such a case can occur in complex floats, for example.)

This problem manifests itself as a missing DW_OP_piece operation after
the last fragment. This happens because the function for printing
constant float value skips printing the accompanying DWARF expression,
as that would also print DW_OP_stack_value (which is not desirable in
this case). However, this also results in DW_OP_piece being skipped.

The reason that DW_OP_piece is missing only for the last piece is that
the act of printing the next fragment corrects this. However, it does
that for the wrong reason -- the code emitting this DW_OP_piece thinks
that the previous fragment was missing, and so it thinks that it needs
to skip over it in order to be able to print itself.

In a simple scenario this works out, but it's likely that in a more
complex setup (where some pieces are in fact missing), this logic would
go badly wrong. In a simple setup gdb also seems to not mind the fact
that the DW_OP_piece is missing, but it would also likely not handle
more complex use cases.

For this reason, this patch disables the usage of DW_OP_implicit_value
in the frament scenario (we will use DW_OP_const*** instead), until we
figure out the right way to deal with this. This guarantees that we
produce valid expressions, and gdb can handle both kinds of inputs
anyway.

Differential Revision: https://reviews.llvm.org/D92013
2020-12-22 10:07:47 +01:00
David Spickett
ca7a8a5db4 [llvm][ARM/AArch64] Convert Target Parser CPU tests to fixtures
Also convert the test function to use EXPECT_EQ and
remove the special case for the AEK_NONE extension.

This means that each test is marked as failing separatley
and the accumultated EXPECT failures are printed next
to that test, with its parameters.

Before they would be hidden by the "pass &=" pattern
and failures would print in one block since it was a
"single" test.

Example of the new failure messages:
```
ARMCPUTestsPart1/ARMCPUTestFixture.ARMCPUTests/6
[==========] Running 1 test from 1 test case.
[----------] Global test environment set-up.
[----------] 1 test from ARMCPUTestsPart1/ARMCPUTestFixture
[ RUN      ] ARMCPUTestsPart1/ARMCPUTestFixture.ARMCPUTests/6
/work/open_source/nightly-llvm/llvm-project/llvm/unittests/Support/TargetParserTest.cpp:66:
Failure
      Expected: params.ExpectedFlags
      Which is: 3405705229
To be equal to: default_extensions
      Which is: 1
[  FAILED  ] ARMCPUTestsPart1/ARMCPUTestFixture.ARMCPUTests/6, where
GetParam() = "arm8", "armv4", "none", 0xcafef00d, "4" (0 ms)
```

Reviewed By: MarkMurrayARM

Differential Revision: https://reviews.llvm.org/D93392
2020-12-22 09:07:20 +00:00
sameeran joshi
fbe8dbe091 [Flang][openmp][5/5] Make dist_schedule clause part of OmpClause
After discussion in `D93482` we found that the some of the clauses were not
following the common OmpClause convention.

The benefits of using OmpClause:
- Functionalities from structure checker are mostly aligned to work with
  `llvm::omp::Clause`.
- The unparsing as well can take advantage.
- Homogeneity with OpenACC and rest of the clauses in OpenMP.
- Could even generate the parser with TableGen, when there is homogeneity.
- It becomes confusing when to use `flangClass` and `flangClassValue` inside
  TableGen, if incase we generate parser using TableGen we could have only a
  single `let expression`.

This patch makes `OmpDistScheduleClause` clause part of `OmpClause`.
The unparse function for `OmpDistScheduleClause` is adapted since the keyword
and parenthesis are issued by the corresponding unparse function for
`parser::OmpClause::DistSchedule`.

Reviewed By: clementval, kiranktp

Differential Revision: https://reviews.llvm.org/D93644
2020-12-22 14:32:33 +05:30
sameeran joshi
4a13143c75 [Flang][openmp][4/5] Make nowait clause part of OmpClause
After discussion in `D93482` we found that the some of the clauses were not
following the common OmpClause convention.

The benefits of using OmpClause:
- Functionalities from structure checker are mostly aligned to work with
  `llvm::omp::Clause`.
- The unparsing as well can take advantage.
- Homogeneity with OpenACC and rest of the clauses in OpenMP.
- Could even generate the parser with TableGen, when there is homogeneity.
- It becomes confusing when to use `flangClass` and `flangClassValue` inside
  TableGen, if incase we generate parser using TableGen we could have only a
  single `let expression`.

This patch makes `OmpNoWait` clause part of `OmpClause`.

Reviewed By: clementval, kiranktp

Differential Revision: https://reviews.llvm.org/D93643
2020-12-22 14:02:19 +05:30
Gil Rapaport
29d94856cb [LV] Avoid needless fold tail
When the trip-count is provably divisible by the maximal/chosen VF, folding the
loop's tail during vectorization is redundant. This commit extends the existing
test for constant trip-counts to any trip-count known to be divisible by
maximal/selected VF by SCEV.

Differential Revision: https://reviews.llvm.org/D93615
2020-12-22 10:25:20 +02:00
sameeran joshi
f7a5280f64 [Flang][openmp][3/5] Make ProcBind clause part of OmpClause
After discussion in `D93482` we found that the some of the clauses were not
following the common OmpClause convention.

The benefits of using OmpClause:
- Functionalities from structure checker are mostly aligned to work with
  `llvm::omp::Clause`.
- The unparsing as well can take advantage.
- Homogeneity with OpenACC and rest of the clauses in OpenMP.
- Could even generate the parser with TableGen, when there is homogeneity.
- It becomes confusing when to use `flangClass` and `flangClassValue` inside
  TableGen, if incase we generate parser using TableGen we could have only a
  single `let expression`.

This patch makes `OmpProcBindClause` clause part of `OmpClause`.
The unparse function is dropped as the unparsing is done by `WALK_NESTED_ENUM`
for `OmpProcBindClause`.

Reviewed By: clementval, kiranktp

Differential Revision: https://reviews.llvm.org/D93642
2020-12-22 13:40:38 +05:30
sameeran joshi
f1474a4f31 [Flang][openmp][2/5] Make Default clause part of OmpClause
After discussion in `D93482` we found that the some of the clauses were not
following the common OmpClause convention.

The benefits of using OmpClause:
- Functionalities from structure checker are mostly aligned to work with
  `llvm::omp::Clause`.
- The unparsing as well can take advantage.
- Homogeneity with OpenACC and rest of the clauses in OpenMP.
- Could even generate the parser with TableGen, when there is homogeneity.
- It becomes confusing when to use `flangClass` and `flangClassValue` inside
  TableGen, if incase we generate parser using TableGen we could have only a
  single `let expression`.

This patch makes `OmpDefaultClause` clause part of `OmpClause`.
The unparse function is dropped as the unparsing is done by `WALK_NESTED_ENUM`
for `OmpDefaultClause`.

Reviewed By: clementval, kiranktp

Differential Revision: https://reviews.llvm.org/D93641
2020-12-22 13:17:44 +05:30
sameeran joshi
5a58d3eafe [Flang][openmp][1/5] Make Allocate clause part of OmpClause
After discussion in `D93482` we found that the some of the clauses were not
following the common OmpClause convention.

The benefits of using OmpClause:
- Functionalities from structure checker are mostly aligned to work with
  `llvm::omp::Clause`.
- The unparsing as well can take advantage.
- Homogeneity with OpenACC and rest of the clauses in OpenMP.
- Could even generate the parser with TableGen, when there is homogeneity.
- It becomes confusing when to use `flangClass` and `flangClassValue` inside
  TableGen, if incase we generate parser using TableGen we could have only a
  single `let expression`.

This patch makes `allocate` clause part of `OmpClause`.The unparse function for
`OmpAllocateClause` is adapted since the keyword and parenthesis are issued by
the corresponding unparse function for `parser::OmpClause::Allocate`.

Reviewed By: clementval

Differential Revision: https://reviews.llvm.org/D93640
2020-12-22 12:53:34 +05:30
Hsiangkai Wang
cffdb541a0 [RISCV] Define vector compare intrinsics.
Define vector compare intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93368
2020-12-22 14:08:18 +08:00
Zakk Chen
6ce4740b5d [RISCV] Define vleff intrinsics.
Define vleff intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93516
2020-12-21 22:05:38 -08:00
Bing1 Yu
0e54092394 [LegalizeType] When LegalizeType procedure widens a masked_gather, set MemoryType's EltNum equal to Result's EltNum
When LegalizeType procedure widens a masked_gather, set MemoryType's EltNum equal to Result's EltNum.

As I mentioned in https://reviews.llvm.org/D91092, in previous code, If we have a v17i32's masked_gather in avx512, we widen it to a v32i32's masked_gather with a v17i32's MemoryType. When the SplitVecRes_MGATHER process this v32i32's masked_gather, GetSplitDestVTs will assert fail since what you are going to split is v17i32.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93610
2020-12-22 13:27:38 +08:00
Zi Xuan Wu
6c04bbc435 [CSKY 3/n] Add bare-bones C-SKY MCTargetDesc
Add basis of CSKY MCTargetDesc and it's enough to compile and link but doesn't yet do anything particularly useful.
Once an ASM parser and printer are added in the next two patches, the whole thing can be usefully tested.

Differential Revision: https://reviews.llvm.org/D93372
2020-12-22 11:32:39 +08:00