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347bd5fb6f
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154 Commits

Author SHA1 Message Date
Chris Lattner
347bd5fb6f Remove noncopyableV base classes, as they were confusing the doxygen documentation, 
making it harder to read.

llvm-svn: 6575
 2003-06-03 15:28:40 +00:00
Vikram S. Adve
9625e27034 Made a single common InvalidRegNum = -1. 
llvm-svn: 6473
 2003-05-31 07:44:07 +00:00
Misha Brukman
ef428e8dca Fixed misspelling and broke a line that was wrapping. 
llvm-svn: 6391
 2003-05-29 05:00:14 +00:00
Misha Brukman
2f45624868 Allow allocation of a Sparc TargetMachine. 
llvm-svn: 6364
 2003-05-27 21:46:07 +00:00
Vikram S. Adve
73ee5ff6b8 (1) Added special register class containing (for now) %fsr. 
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

llvm-svn: 6343
 2003-05-27 00:07:13 +00:00
Vikram S. Adve
e3af518f95 Make case of GetNumOfInt/FloatArgRegs functions to be use lower case 
like all the other functions.

llvm-svn: 6326
 2003-05-25 16:02:05 +00:00
Misha Brukman
6ffaa5b188 Reword to remove reference to how things worked in the past. 
llvm-svn: 6323
 2003-05-24 01:08:43 +00:00
Misha Brukman
151f7484ab NOP instructions are pseudo-instructions. We should not have them explicitly in 
our representation, since they are usually special cases of already-existing
instructions.

This abstracts away methods that let a pass create and verify a NOP instruction,
without relying on a `NOP' enum to be in existence in the target's instruction
info descriptor.

llvm-svn: 6319
 2003-05-24 00:08:39 +00:00
Chris Lattner
bbe1aba425 Remove two fields from TargetData which are target specific. 
llvm-svn: 5963
 2003-04-26 20:11:09 +00:00
Chris Lattner
a550ee6b5d Fix method name type-o 
llvm-svn: 5933
 2003-04-25 05:23:27 +00:00
Chris Lattner
a106185aa1 Default ctor doesn't provide name 
llvm-svn: 5921
 2003-04-25 02:50:19 +00:00
Chris Lattner
55a4aea29b Add new targetdata ctor to create a targetdata appropriate to the module 
llvm-svn: 5902
 2003-04-24 19:08:45 +00:00
Misha Brukman
71aef01e7e Must use std::pair instead of just 'pair'. 
llvm-svn: 5767
 2003-04-07 00:25:09 +00:00
Guochun Shi
59e61c4ce2 added a function and a member to the TargetSchedInfo class 
which is used  by Modulo Scheduling pass

llvm-svn: 5766
 2003-04-07 00:00:36 +00:00
Chris Lattner
eac243c414 Simplify the interface 
llvm-svn: 5313
 2003-01-15 21:13:32 +00:00
Chris Lattner
b27d60ccf1 Rename MachineInstrInfo -> TargetInstrInfo 
llvm-svn: 5272
 2003-01-14 22:00:31 +00:00
Chris Lattner
ab69d9da2f Move annotation to support library 
llvm-svn: 5268
 2003-01-14 21:29:58 +00:00
Chris Lattner
8decb3e453 Rename MachineInstrInfo -> TargetInstrInfo 
llvm-svn: 5214
 2003-01-13 00:21:32 +00:00
Chris Lattner
5fd0d8f44b * Start renaming MachineInstrInfo -> TargetInstrInfo 
* Add new M_TERMINATOR_FLAG

llvm-svn: 5213
 2003-01-13 00:21:19 +00:00
Chris Lattner
2117077d8f Add new getName method 
llvm-svn: 5212
 2003-01-13 00:19:44 +00:00
Chris Lattner
dfa3c21f1c More renamings of Target/Machine*Info to Target/Target*Info 
llvm-svn: 5204
 2002-12-29 03:13:05 +00:00
Chris Lattner
bff4411f3a Rename MachineOptInfo to TargetoptInfo 
Rename MachineCacheInfo to TargetCacheInfo

llvm-svn: 5203
 2002-12-29 02:50:35 +00:00
Chris Lattner
c3dbf62971 * doxygenize comment 
* rename MachineFrameInfo to TargetFrameInfo

llvm-svn: 5170
 2002-12-28 20:13:29 +00:00
Chris Lattner
90d1ea29ab Sparc specific methods default to abort rather than being pure virtual 
llvm-svn: 5169
 2002-12-28 20:12:54 +00:00
Chris Lattner
51c7c172db Expose some very simple information about the frame, rather than in-depth 
target specific information.  Rename MachineFrameInfo to TargetFrameInfo

llvm-svn: 5168
 2002-12-28 20:12:10 +00:00
Chris Lattner
b525ce97cc * Keep track of register alignment as well as register size 
* Add comments
* Add a new allocation_order iterator for register classes which targets may
  use to control the register order and available registers based on properties
  of the function being compiled.
* Remove access to FP and SP registers
* Add new callframe setup opcode support
* Eliminate moveImm2Reg method
* Revamp frame offset handling and prolog/epilog code generation

llvm-svn: 5167
 2002-12-28 20:10:23 +00:00
Chris Lattner
881ffece47 Simplify spill interface methods 
llvm-svn: 5142
 2002-12-25 05:02:00 +00:00
Chris Lattner
b44ebe2588 Add comment 
llvm-svn: 5141
 2002-12-25 05:01:46 +00:00
Chris Lattner
bc5e71ef2f Allow the target machines to specify endianness and pointer size 
llvm-svn: 5128
 2002-12-24 00:02:17 +00:00
Chris Lattner
079d149fbd Simplify interface to remove virtual function references 
llvm-svn: 5100
 2002-12-17 04:20:39 +00:00
Chris Lattner
3b7f709ebd Add support for register alias set description 
llvm-svn: 5080
 2002-12-16 16:39:14 +00:00
Chris Lattner
07cc730ddd Export well known instruction opcodes usable by target independant passes 
llvm-svn: 5063
 2002-12-15 22:16:08 +00:00
Chris Lattner
4214ac384a Simplify interfaces used by regalloc to insert code 
llvm-svn: 5052
 2002-12-15 20:06:35 +00:00
Chris Lattner
9b1957fd1e Simplify TargetRegisterClass a bit, also eliminating virtual function call 
overhead

llvm-svn: 5049
 2002-12-15 19:29:14 +00:00
Chris Lattner
51cf15cf12 * Rename const_regclass_begin/end to just regclass_begin/end 
* Regclass iterators need an extra level of pointerness to work right
* Pull inverse mapping code out of target description files

llvm-svn: 5046
 2002-12-15 18:40:01 +00:00
Misha Brukman
fb02408496 Added moveReg2Reg() and moveImm2Reg() to accomodate moving data around due to 
PHI nodes.

llvm-svn: 5001
 2002-12-13 09:54:12 +00:00
Misha Brukman
bc60f65211 Define the 2-address flag used by X86 instructions (add,sub,and,or,xor) that 
need to be declared as such.

llvm-svn: 4975
 2002-12-12 23:19:51 +00:00
Misha Brukman
32ec427192 Added prototypes for emitting prologue and epilogue for function code 
generation.

llvm-svn: 4927
 2002-12-04 23:55:56 +00:00
Misha Brukman
101076f586 storeReg2RegOffset() and loadRegOffset2Reg() now take the iterator by value 
instead of by reference, since they return the modified iterator.

llvm-svn: 4914
 2002-12-04 17:14:13 +00:00
Misha Brukman
6e1c4851ea Moved buildReg2RegClassMap() into from X86RegisterInfo to MRegisterInfo, since 
it is target-independent.

llvm-svn: 4911
 2002-12-04 16:47:04 +00:00
Chris Lattner
aeb454c30e Expose target data through a method for uniformity 
llvm-svn: 4901
 2002-12-04 05:20:12 +00:00
Misha Brukman
6b9cb74fdc RegisterInfo now supports handing out caller- and callee-save registers, as 
well as building a map from a physical register to its register class.

llvm-svn: 4896
 2002-12-03 23:09:53 +00:00
Chris Lattner
866d635098 Add entries to track information about implicit uses and definitions of 
the instructions

llvm-svn: 4875
 2002-12-03 05:41:32 +00:00
Chris Lattner
920d619d39 The hopefully final version of addPassesToEmitMachineCode which does not 
have any question about ownership

llvm-svn: 4863
 2002-12-02 21:15:42 +00:00
Chris Lattner
b7073c8c07 Add comment about ownership semantics 
llvm-svn: 4859
 2002-12-02 21:13:45 +00:00
Chris Lattner
9872f53512 Add stub to emit machine code for JIT 
llvm-svn: 4856
 2002-12-02 21:00:50 +00:00
Misha Brukman
32d007461d Added virtual functions for storing and retrieving values from the stack. 
llvm-svn: 4824
 2002-11-22 22:41:23 +00:00
Misha Brukman
45b9648b91 MRegisterInfo.h - Added prototypes for functions we need to map a register to 
an appropriate TargetRegisterClass, also adds TargetRegisterClass definition.
TargetMachine.h - speling.

llvm-svn: 4781
 2002-11-20 18:54:53 +00:00
Chris Lattner
e138d4fbc8 Make sure that print gets a targetmachine 
CVS: ----------------------------------------------------------------------

llvm-svn: 4735
 2002-11-17 23:21:45 +00:00
Chris Lattner
9971426ca0 Add machine independant printer interface 
llvm-svn: 4729
 2002-11-17 22:54:55 +00:00