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Author SHA1 Message Date
Evan Cheng
36170e63a3 ldm / stm instruction encodings. 
llvm-svn: 55599
 2008-09-01 07:48:18 +00:00
Evan Cheng
01019d7909 AXI2 and AXI3 instruction encodings. 
llvm-svn: 55598
 2008-09-01 07:34:13 +00:00
Evan Cheng
fdae49e627 Reorganize instruction formats again; AXI1 encoding. 
llvm-svn: 55597
 2008-09-01 07:19:00 +00:00
Evan Cheng
26305b192f addrmode3 instruction encodings. 
llvm-svn: 55596
 2008-09-01 07:00:14 +00:00
Evan Cheng
eb40cb3e42 Reorganize some instruction format definitions. No functionality change. 
llvm-svn: 55594
 2008-09-01 01:51:14 +00:00
Evan Cheng
fa095aec1e Rest of addrmode2 instruction encodings. 
llvm-svn: 55593
 2008-09-01 01:27:33 +00:00
Evan Cheng
4c8338c0d3 Addr2 word / byte load encodings. 
llvm-svn: 55591
 2008-08-31 19:02:21 +00:00
Evan Cheng
94f3d276c6 Addr1 instructions opcodes are encoded in bits 21-24; encode S bit. 
llvm-svn: 55590
 2008-08-31 18:32:16 +00:00
Gabor Greif
7db742d8c2 fix a bunch of 80-col violations 
llvm-svn: 55588
 2008-08-31 15:37:04 +00:00
Bill Wendling
297eb080b6 Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR 
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.

llvm-svn: 55582
 2008-08-31 02:59:23 +00:00
Bill Wendling
8faa2f3ec4 Expand for ROTR with MVT::i64. 
Dale, Could you please review this?

llvm-svn: 55581
 2008-08-31 02:53:19 +00:00
Bill Wendling
5c442aafb6 CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG 
combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.

llvm-svn: 55579
 2008-08-31 02:32:12 +00:00
Bill Wendling
4a9ded80e2 Cosmetic changes to Machine LICM. No functionality change. 
llvm-svn: 55578
 2008-08-31 02:30:23 +00:00
Bill Wendling
3f918b3603 Another situation where ROTR is cheaper than ROTL. 
llvm-svn: 55577
 2008-08-31 01:13:31 +00:00
Bill Wendling
ef64d4333e For this pattern, ROTR is the cheaper option. 
llvm-svn: 55576
 2008-08-31 01:04:56 +00:00
Bill Wendling
08690f06b2 - Fix comment so that it describes how the code really works: 
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotl x, y)
   // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotr x, (sub 32, y))

Example: (x == 0xDEADBEEF and y == 4)

    (x << 4) | (x >> 28)
 => 0xEADBEEF0 | 0x0000000D
 => 0xEADBEEFD

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => 0xEADBEEFD

- Fix comment and code for second version. It wasn't using the rot* propertly.

   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 
   //   (rotr x, y)
   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
   //   (rotl x, (sub 32, y))

    (x << 28) | (x >> 4)
 => 0xD0000000 | 0x0DEADBEE
 => 0xDDEADBEE

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => (0xEADBEEFD)

llvm-svn: 55575
 2008-08-31 00:37:27 +00:00
Gabor Greif
fa6e220233 typo 
llvm-svn: 55574
 2008-08-30 22:16:05 +00:00
Gabor Greif
2aef1d5e4c fix some 80-col violations 
llvm-svn: 55571
 2008-08-30 19:29:20 +00:00
Gordon Henriksen
3324b5c3ca PR2731: C and Ocaml bindings for setTailCall and isTailCall. 
Based on patch by Giorgos Korfiatis.

llvm-svn: 55570
 2008-08-30 16:34:54 +00:00
Gordon Henriksen
3a9a0e274b Fix ConstantExpr::getInsertElement. 
Breakage was exposed in the Ocaml bindings tests after Chris
uncommented an assertion in r55084.

llvm-svn: 55566
 2008-08-30 15:41:51 +00:00
Gabor Greif
8fa04b6eb0 fix some 80-col violations 
llvm-svn: 55565
 2008-08-30 10:09:02 +00:00
Evan Cheng
b40b710766 Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction. 
llvm-svn: 55564
 2008-08-30 09:09:33 +00:00
Evan Cheng
4cfcf9ca51 Fold isRematerializable checks into isSafeToReMat. 
llvm-svn: 55563
 2008-08-30 09:07:18 +00:00
Evan Cheng
c3c439a624 For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these. 
llvm-svn: 55562
 2008-08-30 08:54:22 +00:00
Evan Cheng
4bc8c9652e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). 
llvm-svn: 55558
 2008-08-30 02:03:58 +00:00
Daniel Dunbar
767a0be71c Enable -fvisibility-inlines-hidden by default for compilers which 
support it.

llvm-svn: 55557
 2008-08-30 01:16:19 +00:00
Dale Johannesen
0124a7db51 Testcases for ppc atomics. 
llvm-svn: 55556
 2008-08-30 00:54:31 +00:00
Owen Anderson
6c8f04643e Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg 
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.

llvm-svn: 55555
 2008-08-30 00:38:46 +00:00
Dale Johannesen
1cfbb25e75 Add ppc partial-word ATOMIC_CMP_SWAP. 
llvm-svn: 55554
 2008-08-30 00:08:53 +00:00
Evan Cheng
c1c53221c5 Swap fp comparison operands and change predicate to allow load folding (safely this time). 
llvm-svn: 55553
 2008-08-29 23:22:12 +00:00
Evan Cheng
a884330e08 Use static_cast instead of C style cast. 
llvm-svn: 55552
 2008-08-29 23:21:31 +00:00
Evan Cheng
9ee227f1df Fix 80 col. violations. 
llvm-svn: 55551
 2008-08-29 23:20:46 +00:00
Evan Cheng
79d2a8f97d xfail this. 
llvm-svn: 55550
 2008-08-29 22:59:13 +00:00
Evan Cheng
2a3e05b519 Back out 55498. It broken Apple style bootstrapping. 
llvm-svn: 55549
 2008-08-29 22:21:44 +00:00
Evan Cheng
17382f9ffb Backing out 55521. Not safe. 
llvm-svn: 55548
 2008-08-29 22:13:21 +00:00
Dale Johannesen
bc977ce106 Add partial word version of ATOMIC_SWAP. 
llvm-svn: 55546
 2008-08-29 18:29:46 +00:00
Owen Anderson
3aa3841da2 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
llvm-svn: 55545
 2008-08-29 17:45:56 +00:00
Chris Lattner
a90998343b regenerate 
llvm-svn: 55542
 2008-08-29 17:20:18 +00:00
Chris Lattner
efbbbb0cde Asmprint nameless instructions as: 
%4 = add ...

instead of:

add ...    ; 4

This makes opt -print-cfg output actually usable and makes .ll files
generally easier to read.  This fixes PR2480

llvm-svn: 55541
 2008-08-29 17:19:30 +00:00
Chris Lattner
f24550c9d2 allow this to pass. 
llvm-svn: 55540
 2008-08-29 17:18:26 +00:00
Chris Lattner
b23f7dae39 Add support for parsing .ll files that have numbers in front of 
nameless values, such as:

%3 = add i32 4, 2

This fixes the first half of PR2480

llvm-svn: 55539
 2008-08-29 17:12:13 +00:00
Evan Cheng
3fb02ae0b6 TableGen'ing instruction encodings. 
llvm-svn: 55533
 2008-08-29 07:42:03 +00:00
Evan Cheng
b38decd917 addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode. 
llvm-svn: 55531
 2008-08-29 07:40:52 +00:00
Evan Cheng
5150e3da45 MVN is addrmode1. 
llvm-svn: 55530
 2008-08-29 07:36:24 +00:00
Daniel Dunbar
8a2cc13fb3 Add GlobalValue::{removeFromParent,eraseFromParent} 
llvm-svn: 55529
 2008-08-29 07:30:15 +00:00
Evan Cheng
f90bc9a050 More refactoring. 
llvm-svn: 55528
 2008-08-29 06:41:12 +00:00
Daniel Dunbar
1b3e44db87 Add DenseMap::lookup: 
/// lookup - Return the entry for the specified key, or a default
  /// constructed value if no such entry exists.

llvm-svn: 55523
 2008-08-29 00:48:44 +00:00
Evan Cheng
cdd06ba3f4 Swap fp comparison operands and change predicate to allow load folding. 
llvm-svn: 55521
 2008-08-28 23:48:31 +00:00
Evan Cheng
c50df85672 Refactor ARM instruction format definitions into a separate file. No functionality changes. 
llvm-svn: 55518
 2008-08-28 23:39:26 +00:00
Dan Gohman
c7b8401b77 Add a target callback for FastISel. 
llvm-svn: 55512
 2008-08-28 23:21:34 +00:00