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Commit Graph

34 Commits

Author SHA1 Message Date
Bill Wendling
26eb9fb1e0 We only need to specify the most-implied feature for an architecture.
llvm-svn: 37275
2007-05-22 05:15:37 +00:00
Bill Wendling
88e78f8bdb 3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX.
llvm-svn: 36860
2007-05-06 07:56:19 +00:00
Bill Wendling
dc82c5a195 Add an "implies" field to features. This indicates that, if the current
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.

llvm-svn: 36756
2007-05-04 20:38:40 +00:00
Bill Wendling
552e4ff1be Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers
clobbered by a call.

llvm-svn: 36448
2007-04-25 21:31:48 +00:00
Bill Wendling
3b1189afbf Add support for our first SSSE3 instruction "pmulhrsw".
llvm-svn: 35869
2007-04-10 22:10:25 +00:00
Chris Lattner
948965f809 Add a description of the X86-64 calling convention and the return
conventions.  This doesn't do anything yet, but may in the future.

llvm-svn: 34636
2007-02-26 18:17:14 +00:00
Evan Cheng
9ce3d493f0 Still need to support -mcpu=<> or cross compilation will fail. Doh.
llvm-svn: 30764
2006-10-06 09:17:41 +00:00
Evan Cheng
6fc0ae2136 Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support.
llvm-svn: 30763
2006-10-06 08:21:07 +00:00
Evan Cheng
15dd42884e Committing X86-64 support.
llvm-svn: 30177
2006-09-08 06:48:29 +00:00
Evan Cheng
d49a6d7065 ImmMask should be 3 for a two-bit field; Compact X86II
llvm-svn: 28381
2006-05-18 06:27:15 +00:00
Evan Cheng
667b133ab9 getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
Evan Cheng
ea24815aa3 Remove PointerType from class Target
llvm-svn: 28368
2006-05-17 21:20:27 +00:00
Evan Cheng
ef93bdc0cf - Use xor to clear integer registers (set R, 0).
- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.

llvm-svn: 25872
2006-02-01 06:13:50 +00:00
Chris Lattner
5587b270e4 * Fix 80-column violations
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854
2006-01-31 19:43:35 +00:00
Jeff Cohen
28a7bd94c9 Fix typo.
llvm-svn: 25760
2006-01-29 03:45:35 +00:00
Evan Cheng
5891f49c47 x86 CPU detection and proper subtarget support
llvm-svn: 25679
2006-01-27 08:10:46 +00:00
Chris Lattner
20d4194a0d PHI and INLINEASM are now built-in instructions provided by Target.td
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
Evan Cheng
670dc80530 Added preliminary x86 subtarget support.
llvm-svn: 25645
2006-01-26 09:53:06 +00:00
Nate Begeman
957e0e7c9e Get closer to fully working scalar FP in SSE regs. This gets singlesource
working, and Olden/power.

llvm-svn: 22441
2005-07-15 00:38:55 +00:00
Nate Begeman
e5314eb2c2 First round of support for doing scalar FP using the SSE2 ISA extension and
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340
2005-07-06 18:59:04 +00:00
Chris Lattner
8d44dcca97 Add support for the -x86-asm-syntax flag, which can be used to choose between
Intel and AT&T style assembly language.  The ultimate goal of this is to
eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission
is not fully operational.

llvm-svn: 16639
2004-10-03 20:36:57 +00:00
Chris Lattner
5e7e9b6c26 Remove a bunch of ad-hoc target-specific flags that were only used by the
old asmprinter.

llvm-svn: 15660
2004-08-11 07:12:04 +00:00
Chris Lattner
90a4b737dd Eliminate 3 of the X86 printImplicit* flags.
llvm-svn: 15398
2004-08-01 08:23:17 +00:00
Chris Lattner
e8e60bf45f Add support for the printImplicitDefsBefore flag
llvm-svn: 12893
2004-04-13 17:18:39 +00:00
John Criswell
f6b16ea70b Added the llvm.readport and llvm.writeport intrinsics for x86. These do
I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.

llvm-svn: 12782
2004-04-08 20:31:47 +00:00
Chris Lattner
e4fa3010db Add FP conditional move instructions, which annoyingly have special properties
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)

llvm-svn: 12574
2004-03-31 22:02:13 +00:00
Alkis Evlogimenos
f208a0fd81 Each instruction now has both an ImmType and a MemType. This describes
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
2004-02-28 22:02:05 +00:00
John Criswell
de34542f41 Added LLVM copyright header.
llvm-svn: 9321
2003-10-21 15:17:13 +00:00
Chris Lattner
07a484e6f6 Completely eliminate the isVoid TSFlag, shifting over all other fields
llvm-svn: 7636
2003-08-06 15:32:20 +00:00
Chris Lattner
f62d020c88 There is nothing special about noops anymore
llvm-svn: 7568
2003-08-04 05:11:37 +00:00
Chris Lattner
0d7b042206 transition to using let instead of set
llvm-svn: 7564
2003-08-04 04:59:56 +00:00
Chris Lattner
89b4a26e56 Add new TableGen instruction definitions
llvm-svn: 7537
2003-08-03 21:54:21 +00:00
Chris Lattner
7ef512fec1 Add Target class for X86 target
llvm-svn: 7523
2003-08-03 18:19:37 +00:00
Chris Lattner
0891dd9161 Initial checkin of X86.td file
llvm-svn: 7510
2003-08-03 15:47:49 +00:00