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Author SHA1 Message Date
Jakob Stoklund Olesen
03856151db Simplify AggressiveAntiDepBreaker's use of register aliases. 
llvm-svn: 121805
 2010-12-14 23:23:15 +00:00
Jakob Stoklund Olesen
870fbdd686 Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet. 
llvm-svn: 121801
 2010-12-14 23:10:48 +00:00
Jim Grosbach
1e943cc60d Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
llvm-svn: 121798
 2010-12-14 22:28:03 +00:00
Bill Wendling
213a3d080d Fix comment. 
llvm-svn: 121797
 2010-12-14 22:26:49 +00:00
Bill Wendling
7e589d4753 Multiclassify the LDR/STR encoding patterns. The only functionality difference 
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

llvm-svn: 121794
 2010-12-14 22:10:49 +00:00
Evan Cheng
7e96e67d98 Fix a minor bug in two-address pass. It was missing a commute opportunity. 
regB = move RCX
regA = op regB, regC
RAX  = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
       movl    %edi, %eax
       shlq    $32, %rcx
       leaq    (%rcx,%rax), %rax
=>
       movl    %edi, %eax
       shlq    $32, %rcx
       orq     %rcx, %rax
rdar://8762995

llvm-svn: 121793
 2010-12-14 21:34:53 +00:00
Jim Grosbach
70721628b4 trailing whitespace 
llvm-svn: 121792
 2010-12-14 21:28:29 +00:00
Matt Beaumont-Gay
01264443a8 Move debugging code entirely within DEBUG(). Silences an unused variable 
warning in the opt build.

llvm-svn: 121791
 2010-12-14 21:14:55 +00:00
Jim Grosbach
e84e95e6d2 Refactor a bit for legibility. 
llvm-svn: 121790
 2010-12-14 21:10:47 +00:00
Jim Grosbach
ef58d5968e trailing whitespace. 
llvm-svn: 121789
 2010-12-14 20:46:39 +00:00
Jim Grosbach
13d82ea2b1 Make sure to propagate the predicate operands for LEApcrel to ADR. 
llvm-svn: 121788
 2010-12-14 20:45:47 +00:00
Owen Anderson
4ce4ce2f60 Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions. 
llvm-svn: 121784
 2010-12-14 19:42:53 +00:00
Jakob Stoklund Olesen
c13ce4748e Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew. 
llvm-svn: 121783
 2010-12-14 19:38:49 +00:00
Jakob Stoklund Olesen
c5ad05ca30 Use TRI::printReg instead of AbstractRegisterDescription when printing 
LiveIntervalUnions.

llvm-svn: 121781
 2010-12-14 18:53:47 +00:00
Jakob Stoklund Olesen
d0b2397aaa Add TargetRegisterInfo::printReg() to pretty-print registers. 
llvm-svn: 121780
 2010-12-14 18:53:39 +00:00
Jim Grosbach
25d3e79b23 ARM Fixups relative to thumb functions need to have the low bit of the value 
set for interworking to work properly. rdar://8755956

llvm-svn: 121778
 2010-12-14 18:46:57 +00:00
Jakob Stoklund Olesen
74ba8b77e6 Q.seenAllInterferences() must be called after Q.collectInterferingVRegs(). 
llvm-svn: 121774
 2010-12-14 17:47:36 +00:00
Daniel Dunbar
3f9b9dc852 MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. 
llvm-svn: 121772
 2010-12-14 17:37:16 +00:00
Jim Grosbach
88727a93a8 Trailing whitespace 
llvm-svn: 121769
 2010-12-14 16:25:15 +00:00
Bill Wendling
4fe39bae17 Use the integer scheduling intrinsic for integer loads and stores. 
llvm-svn: 121765
 2010-12-14 12:33:05 +00:00
Chris Lattner
c1aaf52608 - Insert new instructions before DomBlock's terminator, 
which is simpler than finding a place to insert in BB.
 - Don't perform the 'if condition hoisting' xform on certain
   i1 PHIs, as it interferes with switch formation.

This re-fixes "example 7", without breaking the world hopefully.

llvm-svn: 121764
 2010-12-14 08:46:09 +00:00
Chris Lattner
22d4dc5a4d fix two significant issues with FoldTwoEntryPHINode: 
first, it can kick in on blocks whose conditions have been
folded to a constant, even though one of the edges will be
trivially folded.

second, it doesn't clean up the "if diamond" that it just 
eliminated away.  This is a problem because other simplifycfg
xforms kick in depending on the order of block visitation,
causing pointless work.

llvm-svn: 121762
 2010-12-14 08:01:53 +00:00
Chris Lattner
362f9a82c0 remove the instsimplify logic I added in r121754. It is apparently 
breaking the selfhost builds, though I can't fathom how.

llvm-svn: 121761
 2010-12-14 07:53:03 +00:00
Chris Lattner
c2e42269ae clean up logic, convert std::set to SmallPtrSet, handle the case 
when all 2-entry phis are simplified away.

llvm-svn: 121760
 2010-12-14 07:41:39 +00:00
Chris Lattner
8e4194276b tidy up a bit, move DEBUG down to when we commit to doing the transform so we 
don't print it unless the xform happens.

llvm-svn: 121758
 2010-12-14 07:23:10 +00:00
Chris Lattner
811462b2f4 use SimplifyInstruction instead of reimplementing part of it. 
llvm-svn: 121757
 2010-12-14 07:20:29 +00:00
Chris Lattner
e2400eb801 simplify GetIfCondition by using getSinglePredecessor. 
llvm-svn: 121756
 2010-12-14 07:15:21 +00:00
Chris Lattner
8ea88e66dd use AddPredecessorToBlock in 3 places instead of a manual loop. 
llvm-svn: 121755
 2010-12-14 07:09:42 +00:00
Chris Lattner
a87ac36a54 make FoldTwoEntryPHINode use instsimplify a bit, make 
GetIfCondition faster by avoiding pred_iterator.  No
really interesting change.

llvm-svn: 121754
 2010-12-14 07:00:00 +00:00
Chris Lattner
027d572664 remove the dead (and terrible) llvm::RemoveSuccessor function. 
llvm-svn: 121753
 2010-12-14 06:51:55 +00:00
Chris Lattner
d9436ab7d7 improve DEBUG's a bit, switch to eraseFromParent() to simplify 
code a bit, switch from constant folding to instsimplify.

llvm-svn: 121751
 2010-12-14 06:17:25 +00:00
Chris Lattner
093b5b256d reapply my recent change that disables a piece of the switch formation 
work, but fixes 400.perlbmk.

llvm-svn: 121749
 2010-12-14 05:57:30 +00:00
Bill Wendling
61720b79f9 The tLDR et al instructions were emitting either a reg/reg or reg/imm 
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
 2010-12-14 03:36:38 +00:00
Evan Cheng
6a2bed92f5 bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663 
llvm-svn: 121746
 2010-12-14 03:22:07 +00:00
Jakob Stoklund Olesen
d4d3c5dd1e Remove unused vector. 
llvm-svn: 121741
 2010-12-14 00:58:47 +00:00
Jakob Stoklund Olesen
00d6ac22d0 Try reassigning all virtual register interferences, not just those with lower 
spill weight. Filter out fixed registers instead.

Add support for reassigning an interference that was assigned to an alias.

llvm-svn: 121737
 2010-12-14 00:37:49 +00:00
Jakob Stoklund Olesen
ffefd5bd4e Add stub for RAGreedy::trySplit. 
llvm-svn: 121736
 2010-12-14 00:37:44 +00:00
Owen Anderson
c84f8c23b3 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire 
process cleaner.

llvm-svn: 121735
 2010-12-14 00:36:49 +00:00
Owen Anderson
5536134dc4 Fix recent buildbot breakage by pulling SimplifyCFG back to its state as of r121694, the most recent state 
where I'm confident there were no crashes or miscompilations.  XFAIL the test added since then for now.

llvm-svn: 121733
 2010-12-13 23:49:28 +00:00
Jason W Kim
b5cc5dad79 First cut of ARM/MC/ELF PIC relocations. 
Test has fixme, to move to .s -> .o test when AsmParser works better.

llvm-svn: 121732
 2010-12-13 23:16:07 +00:00
Bob Wilson
33e5e902b0 Remove the rest of the *_sfp Neon instruction patterns. 
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

llvm-svn: 121730
 2010-12-13 23:02:37 +00:00
Bob Wilson
b189b77d9b Simplify N2VSPat, removing some unnecessary type arguments. 
llvm-svn: 121729
 2010-12-13 23:02:31 +00:00
Chris Lattner
dcba81d96f temporarily disable part of my previous patch, which causes an iterator invalidation issue, causing a crash on some versions of perlbmk. 
llvm-svn: 121728
 2010-12-13 23:02:19 +00:00
Dan Gohman
1baada041e Update a comment. 
llvm-svn: 121727
 2010-12-13 22:53:18 +00:00
Owen Anderson
af1dde2673 Revert r121721, which broke buildbots. 
llvm-svn: 121726
 2010-12-13 22:51:08 +00:00
Dan Gohman
b187cce266 Reapply r121520, PartialAlias implementation for BasicAA, now that 
memdep is updated to handle it.

llvm-svn: 121725
 2010-12-13 22:50:24 +00:00
Dan Gohman
f4e1d91b8e Update memdep to handle PartialAlias as MayAlias. 
llvm-svn: 121723
 2010-12-13 22:47:57 +00:00
Owen Anderson
c298c8ed4d Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR, 
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.

llvm-svn: 121721
 2010-12-13 22:29:52 +00:00
Bob Wilson
203303291f Delete a line that I forgot to revert previously. 
llvm-svn: 121719
 2010-12-13 22:05:55 +00:00
Bob Wilson
074095ddf2 Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns. 
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns.  The pattern
gets pretty ugly but it seems to work well.  Partial fix for Radar 8711675.

llvm-svn: 121718
 2010-12-13 21:58:05 +00:00
Bob Wilson
56b41f8b81 Use pseudo instructions for 2-register Neon instructions for scalar FP. 
Partial fix for Radar 8711675.

llvm-svn: 121716
 2010-12-13 21:05:52 +00:00
Bob Wilson
9a6d75a499 Remove unused instruction class arguments. 
llvm-svn: 121715
 2010-12-13 21:05:44 +00:00
Evan Cheng
c90b20fb74 Generalize BFI isel lowering a bit. 
llvm-svn: 121714
 2010-12-13 20:32:54 +00:00
Chris Lattner
759d8aa712 add some DEBUG's. 
llvm-svn: 121711
 2010-12-13 19:55:30 +00:00
Owen Anderson
4ec912b842 In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or 
as a "long" direct branch.  While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches.  Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.

llvm-svn: 121710
 2010-12-13 19:31:11 +00:00
Jim Grosbach
9a282f2202 Use 32-bit types for 32-bit values. 
llvm-svn: 121709
 2010-12-13 19:25:46 +00:00
Jim Grosbach
ad058bd082 Trailing whitespace. 
llvm-svn: 121708
 2010-12-13 19:18:13 +00:00
Benjamin Kramer
7f1cdac1e4 Fix sort predicate. qsort(3)'s predicate semantics differ from std::sort's. Fixes PR 8780. 
llvm-svn: 121705
 2010-12-13 18:20:38 +00:00
Chris Lattner
14810c808b Add a couple dag combines to transform mulhi/mullo into a wider multiply 
when the wider type is legal.  This allows us to compile:

define zeroext i16 @test1(i16 zeroext %x) nounwind {
entry:
	%div = udiv i16 %x, 33
	ret i16 %div
}

into:

test1:                                  # @test1
	movzwl	4(%esp), %eax
	imull	$63551, %eax, %eax      # imm = 0xF83F
	shrl	$21, %eax
	ret

instead of:

test1:                                  # @test1
        movw    $-1985, %ax             # imm = 0xFFFFFFFFFFFFF83F
        mulw    4(%esp)
        andl    $65504, %edx            # imm = 0xFFE0
        movl    %edx, %eax
        shrl    $5, %eax
        ret

Implementing rdar://8760399 and example #4 from:
http://blog.regehr.org/archives/320

We should implement the same thing for [su]mul_hilo, but I don't
have immediate plans to do this.

llvm-svn: 121696
 2010-12-13 08:39:01 +00:00
Chris Lattner
0368bf7457 reinstate my patch: the miscompile was caused by an inverted branch in the 
'and' case.

llvm-svn: 121695
 2010-12-13 08:12:19 +00:00
Chris Lattner
caad324345 Completely disable the optimization I added in r121680 until 
I can track down a miscompile.  This should bring the buildbots
back to life

llvm-svn: 121693
 2010-12-13 07:41:29 +00:00
Chris Lattner
324f849088 remove the verbose-asm "constant pool double" comments that we were printing 
for each constant pool entry.  Using WriteTypeSymbolic here takes time
proportional to the size of the module, for each constant pool entry.

This speeds up -verbose-asm llc on 252.eon (a random testcase at my disposal)
from 4.4s to 2.137s.  llc takes 2.11s with asm-verbose off, so this is now a
pretty reasonable cost for verbose comments.

llvm-svn: 121691
 2010-12-13 07:35:47 +00:00
Chris Lattner
5ce3e42d80 Make simplifycfg reprocess newly formed "br (cond1 | cond2)" conditions 
when simplifying, allowing them to be eagerly turned into switches.  This
is the last step required to get "Example 7" from this blog post:
http://blog.regehr.org/archives/320

On X86, we now generate this machine code, which (to my eye) seems better
than the ICC generated code:

_crud:                                  ## @crud
## BB#0:                                ## %entry
	cmpb	$33, %dil
	jb	LBB0_4
## BB#1:                                ## %switch.early.test
	addb	$-34, %dil
	cmpb	$58, %dil
	ja	LBB0_3
## BB#2:                                ## %switch.early.test
	movzbl	%dil, %eax
	movabsq	$288230376537592865, %rcx ## imm = 0x400000017001421
	btq	%rax, %rcx
	jb	LBB0_4
LBB0_3:                                 ## %lor.rhs
	xorl	%eax, %eax
	ret
LBB0_4:                                 ## %lor.end
	movl	$1, %eax
	ret

llvm-svn: 121690
 2010-12-13 07:00:06 +00:00
Chris Lattner
20b9e84c7e make this logic a bit simpler. 
llvm-svn: 121689
 2010-12-13 06:36:51 +00:00
Chris Lattner
74d917e19d split all the guts of SimplifyCFGOpt::run out into one function 
per terminator kind.

llvm-svn: 121688
 2010-12-13 06:25:44 +00:00
Chris Lattner
ea15ce73be fix a bug in r121680 that upset the various buildbots. 
llvm-svn: 121687
 2010-12-13 05:34:18 +00:00
Chris Lattner
1eb2e235c8 refactor the speculative execution logic to be factored into the cond branch code instead of 
doing a cfg search for every block simplified.

llvm-svn: 121686
 2010-12-13 05:26:52 +00:00
Chris Lattner
4b9e3a31b0 simplify a bunch of code. 
llvm-svn: 121685
 2010-12-13 05:20:28 +00:00
Chris Lattner
d79dd057bf move HoistThenElseCodeToIf up to a more logical and efficient-to-handle place. 
llvm-svn: 121684
 2010-12-13 05:15:29 +00:00
Chris Lattner
80f8577d74 move 'MergeBlocksIntoPredecessor' call earlier. Use 
getSinglePredecessor to simplify code.

llvm-svn: 121683
 2010-12-13 05:10:48 +00:00
Chris Lattner
7ad8e06c3b factor new code out to a SimplifyBranchOnICmpChain helper function. 
llvm-svn: 121681
 2010-12-13 05:03:41 +00:00
Chris Lattner
5cbbcc56ad enhance the "change or icmp's into switch" xform to handle one value in an 
'or sequence' that it doesn't understand.  This allows us to optimize
something insane like this:

int crud (unsigned char c, unsigned x)
 {
   if(((((((((( (int) c <= 32 ||
                    (int) c == 46) || (int) c == 44)
                  || (int) c == 58) || (int) c == 59) || (int) c == 60)
               || (int) c == 62) || (int) c == 34) || (int) c == 92)
            || (int) c == 39) != 0)
     foo();
 }

into:

define i32 @crud(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
entry:
  %cmp = icmp ult i8 %c, 33
  br i1 %cmp, label %if.then, label %switch.early.test

switch.early.test:                                ; preds = %entry
  switch i8 %c, label %if.end [
    i8 39, label %if.then
    i8 44, label %if.then
    i8 58, label %if.then
    i8 59, label %if.then
    i8 60, label %if.then
    i8 62, label %if.then
    i8 46, label %if.then
    i8 92, label %if.then
    i8 34, label %if.then
  ]

by pulling the < comparison out ahead of the newly formed switch.

llvm-svn: 121680
 2010-12-13 04:50:38 +00:00
Chris Lattner
f6be61e969 merge two very similar functions into one that has a bool argument. 
llvm-svn: 121678
 2010-12-13 04:26:26 +00:00
Evan Cheng
190ff7fa88 Disable auto-detection of AVX support since AVX codegen support is not ready. 
llvm-svn: 121677
 2010-12-13 04:23:53 +00:00
Chris Lattner
003b79e2d3 don't bother handling non-canonical icmp's 
llvm-svn: 121676
 2010-12-13 04:18:32 +00:00
Chris Lattner
9bd0b12342 inline a function, making the result much simpler. 
llvm-svn: 121675
 2010-12-13 04:15:19 +00:00
Chris Lattner
25b642edfd Fix my previous patch to handle a degenerate case that the llvm-gcc 
bootstrap buildbot tripped over.

llvm-svn: 121674
 2010-12-13 03:43:57 +00:00
Chris Lattner
9b089512e9 convert some methods to be static functions 
llvm-svn: 121673
 2010-12-13 03:30:12 +00:00
Chris Lattner
46cc5158bb zap two more std::sorts. 
llvm-svn: 121672
 2010-12-13 03:24:30 +00:00
Chris Lattner
a21c02e807 fix a fairly serious oversight with switch formation from 
or'd conditions.  Previously we'd compile something like this:

int crud (unsigned char c) {
   return c == 62 || c == 34 || c == 92;
}

into:

  switch i8 %c, label %lor.rhs [
    i8 62, label %lor.end
    i8 34, label %lor.end
  ]

lor.rhs:                                          ; preds = %entry
  %cmp8 = icmp eq i8 %c, 92
  br label %lor.end

lor.end:                                          ; preds = %entry, %entry, %lor.rhs
  %0 = phi i1 [ true, %entry ], [ %cmp8, %lor.rhs ], [ true, %entry ]
  %lor.ext = zext i1 %0 to i32
  ret i32 %lor.ext

which failed to merge the compare-with-92 into the switch.  With this patch
we simplify this all the way to:

  switch i8 %c, label %lor.rhs [
    i8 62, label %lor.end
    i8 34, label %lor.end
    i8 92, label %lor.end
  ]

lor.rhs:                                          ; preds = %entry
  br label %lor.end

lor.end:                                          ; preds = %entry, %entry, %entry, %lor.rhs
  %0 = phi i1 [ true, %entry ], [ false, %lor.rhs ], [ true, %entry ], [ true, %entry ]
  %lor.ext = zext i1 %0 to i32
  ret i32 %lor.ext

which is much better for codegen's switch lowering stuff.  This kicks in 33 times
on 176.gcc (for example) cutting 103 instructions off the generated code.

llvm-svn: 121671
 2010-12-13 03:18:54 +00:00
Chris Lattner
6d4df726a6 simplify code and reduce indentation 
llvm-svn: 121670
 2010-12-13 02:38:13 +00:00
Chris Lattner
134d892049 convert an std::sort to array_pod_sort. 
llvm-svn: 121669
 2010-12-13 02:00:58 +00:00
Chris Lattner
153b680cdd move the "br (X == 0 | X == 1), T, F" -> switch optimization to a new 
location in simplifycfg.  In the old days, SimplifyCFG was never run on
the entry block, so we had to scan over all preds of the BB passed into
simplifycfg to do this xform, now we can just check blocks ending with
a condbranch.  This avoids a scan over all preds of every simplified 
block, which should be a significant compile-time perf win on functions
with lots of edges.  No functionality change.

llvm-svn: 121668
 2010-12-13 01:57:34 +00:00
Chris Lattner
644a93e06b reduce indentation and generally simplify code, no functionality change. 
llvm-svn: 121667
 2010-12-13 01:47:07 +00:00
Chris Lattner
859fad7373 use getFirstNonPHIOrDbg to simplify this code. 
llvm-svn: 121664
 2010-12-13 01:28:06 +00:00
Chris Lattner
6df4d5d88e reduce indentation by using continue, no functionality change. 
llvm-svn: 121662
 2010-12-13 01:11:17 +00:00
Chris Lattner
72f03b62a9 add a note 
llvm-svn: 121656
 2010-12-13 00:15:25 +00:00
Wesley Peck
f842b79b4b Missed some ADDI <-> ADDIK conversions in 121649. 
llvm-svn: 121652
 2010-12-12 22:53:14 +00:00
Wesley Peck
95cebfc460 MBlaze delay slot filler was not capable of using ADDK and variants to fill delay slots. This broke several test cases when 121649 was committed. This fixes the regression. 
llvm-svn: 121650
 2010-12-12 22:22:49 +00:00
Wesley Peck
38688d020c The ADD and ADDK (and all variants) instructions where flip-flopped in the MBlaze backend. This bug fix makes 64-bit math work on the MBlaze backend. 
llvm-svn: 121649
 2010-12-12 22:02:31 +00:00
Tobias Grosser
cd3d63e102 Remove useless dynamic_cast<>(). 
Thanks Peter for pointing me to something that should have never been
committed to the llvm code base.

llvm-svn: 121648
 2010-12-12 21:58:28 +00:00
Wesley Peck
7274c73974 1. Change MBlaze indirect branches to use absolute branch BRALD instead of pc relative branch BRLD. 
2. Make sure that the MBlaze stack is aligned to 4-byte boundaries.
3. Determine frame indexes that should be placed in the callers stack frame, as per the MBlaze ABI, and place them in the correct locations.

llvm-svn: 121639
 2010-12-12 20:52:31 +00:00
Duncan Sands
47a4bbd31d Catch attempts to remove a deleted node from the CSE maps. Better to 
catch this here rather than later after accessing uninitialized memory
etc.  Fires when compiling the testcase in PR8237.

llvm-svn: 121635
 2010-12-12 13:22:50 +00:00
Benjamin Kramer
a638216447 Generalize the and-icmp-select instcombine further by allowing selects of the form 
(x & 2^n) ? 2^m+C : C

we can offset both arms by C to get the "(x & 2^n) ? 2^m : 0" form, optimize the
select to a shift and apply the offset afterwards.

llvm-svn: 121609
 2010-12-11 10:49:22 +00:00
Benjamin Kramer
5a1721f4ac Factor the (x & 2^n) ? 2^m : 0 instcombine into its own method and generalize it 
to catch cases where n != m with a shift.

llvm-svn: 121608
 2010-12-11 09:42:59 +00:00
Evan Cheng
b6773d7e1f (or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056 
llvm-svn: 121606
 2010-12-11 04:11:38 +00:00
Jakob Stoklund Olesen
a523d5f048 Add named timer groups for the different stages of register allocation. 
llvm-svn: 121604
 2010-12-11 00:19:56 +00:00
Jakob Stoklund Olesen
ef80efea1d Move MRI into RegAllocBase. Clean up debug output a bit. 
llvm-svn: 121599
 2010-12-10 23:49:00 +00:00
Jim Grosbach
98dcdf10c2 Add FIXME 
llvm-svn: 121598
 2010-12-10 23:41:10 +00:00
Nick Lewycky
46a6ed1f0f Remove extraneous close parenthesis. 
Fix build breakage.

llvm-svn: 121596
 2010-12-10 23:14:35 +00:00
Nick Lewycky
9afbedbc48 Move variable that's unused in an NDEBUG build inside the DEBUG() macro, fixing 
lib/CodeGen/RegAllocGreedy.cpp:233: error: unused variable 'TRC' [-Wunused-variable]

llvm-svn: 121594
 2010-12-10 23:05:10 +00:00
Owen Anderson
47a78db79b Attempt to get Thumb2 branch fixups working properly. 
llvm-svn: 121593
 2010-12-10 23:02:28 +00:00
Jakob Stoklund Olesen
6cd6e644e7 Force the greedy register allocator to always use the inline spiller. 
Soon, RegAllocGreedy will start splitting live ranges, and then deferred
spilling won't work anyway.

llvm-svn: 121591
 2010-12-10 22:54:44 +00:00
Jakob Stoklund Olesen
cbd4bac09d Rip out live range splitting support from the inline spiller. 
The spiller should only spill. The register allocator will drive live range
splitting, it has the needed information about register pressure and
interferences.

llvm-svn: 121590
 2010-12-10 22:54:40 +00:00
Owen Anderson
8424ab65e2 Fix merge error in my last fix to Thumb2 vldr fixups. 
llvm-svn: 121588
 2010-12-10 22:53:48 +00:00
Owen Anderson
f310c92333 Fixups for Thumb2 vldr's need to have the effective PC aligned as well. 
llvm-svn: 121587
 2010-12-10 22:46:47 +00:00
Bill Wendling
7f1cea7009 The MCFixupKindInfo table needs to be in the order that the enums were 
declared. Add a note specifying this and spruce up the list a bit.

llvm-svn: 121586
 2010-12-10 22:37:19 +00:00
Owen Anderson
e85fabac75 Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends. 
llvm-svn: 121585
 2010-12-10 22:32:08 +00:00
Jakob Stoklund Olesen
5ab6552845 Use AllocationOrder in RegAllocGreedy, fix a bug in the hint calculation. 
llvm-svn: 121584
 2010-12-10 22:21:05 +00:00
Bob Wilson
d30768fe3e Add float patterns for Neon vld1-lane/dup and vst1-lane operations. 
llvm-svn: 121583
 2010-12-10 22:13:32 +00:00
Bob Wilson
ae683e722f Remove unused arguments. 
llvm-svn: 121582
 2010-12-10 22:13:24 +00:00
Owen Anderson
aaf97da84b Fix encoding of Thumb1 LDRB and STRB. 
llvm-svn: 121581
 2010-12-10 22:11:13 +00:00
Jim Grosbach
d7f424dec3 Trailing whitespace. 
llvm-svn: 121580
 2010-12-10 21:57:34 +00:00
Owen Anderson
44ad90c850 Fix Thumb2 encodings of STREX and LDREX. 
llvm-svn: 121579
 2010-12-10 21:52:38 +00:00
Dan Gohman
18e2a55c07 Revert r121520, which may have introduced miscompilations. 
llvm-svn: 121573
 2010-12-10 21:48:28 +00:00
Jim Grosbach
82dd80c956 Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999 
llvm-svn: 121525
 2010-12-10 21:24:18 +00:00
Jim Grosbach
63853d61e1 Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726 
llvm-svn: 121524
 2010-12-10 21:05:07 +00:00
Jim Grosbach
467e860805 More trivial cleanup. No need to define the EncoderMethod property type. Can 
just assign to it.

llvm-svn: 121523
 2010-12-10 20:53:44 +00:00
Jim Grosbach
5696d964ca Tidy up. 
llvm-svn: 121522
 2010-12-10 20:51:35 +00:00
Jim Grosbach
401391235f Trailing whitespace. 
llvm-svn: 121521
 2010-12-10 20:47:29 +00:00
Dan Gohman
d1bf1d8013 Implement PartialAlias checking in BasicAA. 
llvm-svn: 121520
 2010-12-10 20:47:03 +00:00
Jakob Stoklund Olesen
ea59381fc8 Fix miscompilation caused by trivial logic error in the reassignVReg() 
interference check.

llvm-svn: 121519
 2010-12-10 20:45:04 +00:00
Dan Gohman
b0fa0f7849 Minimally update this code to handle PartialAlias. 
llvm-svn: 121518
 2010-12-10 20:14:49 +00:00
Dan Gohman
98f5b2ae22 Use PartialAlias to do better noalias lint checking. 
llvm-svn: 121514
 2010-12-10 20:04:06 +00:00
Dan Gohman
cbee92bb65 Teach AliasAnalysisCounter about PartialAlias. 
llvm-svn: 121513
 2010-12-10 19:53:05 +00:00
Dan Gohman
26e1b4ac11 Teach AliasAnalysisEvaluator about PartialAlias. 
llvm-svn: 121512
 2010-12-10 19:52:40 +00:00
Dan Gohman
9e03ffc789 Update this code to handle PartialAlias as MayAlias. 
llvm-svn: 121508
 2010-12-10 19:40:47 +00:00
Bob Wilson
5ff13f9d5c Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions. 
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed.  Add tests for this, too.

llvm-svn: 121506
 2010-12-10 19:37:42 +00:00
Jim Grosbach
4a414e1973 Teach isCSRestore() that ARM/Thumb2 functions will use post-modify LDR 
instructions to restore a single register rather than an LDM instruction.
rdar://8754999

llvm-svn: 121498
 2010-12-10 18:41:15 +00:00
Jakob Stoklund Olesen
e3924a3c85 Add an AllocationOrder class that can iterate over the allocatable physical 
registers for a given virtual register.

Reserved registers are filtered from the allocation order, and any valid hint is
returned as the first suggestion.

For target dependent hints, a number of arcane target hooks are invoked.

llvm-svn: 121497
 2010-12-10 18:36:02 +00:00
Jim Grosbach
a378c43eae Thumb unconditional branch binary encoding. rdar://8754994 
llvm-svn: 121496
 2010-12-10 18:21:33 +00:00
Jim Grosbach
905301a7d8 Thumb conditional branch binary encodings. rdar://8745367 
llvm-svn: 121493
 2010-12-10 17:13:40 +00:00
Rafael Espindola
0e665e502d Fixed version of 121434 with no new memory leaks. 
llvm-svn: 121471
 2010-12-10 07:39:47 +00:00
Daniel Dunbar
fd96efb8e9 Mach-O: Tweak field name. 
llvm-svn: 121465
 2010-12-10 06:19:39 +00:00
Rafael Espindola
676ea9d9b4 Fix cmake build. 
llvm-svn: 121462
 2010-12-10 04:28:37 +00:00
Rafael Espindola
011e168728 Revert my previous patch to make the valgrind bots happy. 
llvm-svn: 121461
 2010-12-10 04:01:09 +00:00
NAKAMURA Takumi
e3f485b0dc lib/Target/CMakeLists.txt: Add missing lib/Target/TargetAsmInfo.cpp, following up to r121434. 
llvm-svn: 121454
 2010-12-10 02:15:24 +00:00
Kevin Enderby
a2efb1ad4e Fix the leak from r121401 of the Operands erased in the list but not deleted. 
llvm-svn: 121450
 2010-12-10 01:41:56 +00:00
Nate Begeman
8c00ecd290 Add some missing predicates. 
llvm-svn: 121445
 2010-12-10 00:54:26 +00:00
Nate Begeman
cb6d1c8193 Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. 
llvm-svn: 121439
 2010-12-10 00:26:57 +00:00
Rafael Espindola
03ad1e8f1f Initial support for the cfi directives. This is just enough to get 
f:
        .cfi_startproc
        nop
        .cfi_endproc

assembled (on ELF).

llvm-svn: 121434
 2010-12-09 23:48:29 +00:00
Rafael Espindola
ebe4cab1db Use const references. 
llvm-svn: 121426
 2010-12-09 23:08:35 +00:00
Bill Wendling
f8eaf8a243 Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the 
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>

llvm-svn: 121417
 2010-12-09 21:49:07 +00:00
Nate Begeman
4a62a3e229 Add support for AVX to materialize +0.0 when doing scalar FP. 
llvm-svn: 121415
 2010-12-09 21:43:51 +00:00
Owen Anderson
4be3b6db5c Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect, 
but it gets many more of them correct than it did previously.

llvm-svn: 121414
 2010-12-09 21:34:47 +00:00
Stuart Hastings
f7bba0cfe3 Initial support for nested CALLSEQ_START/CALLSEQ_END constructs in LegalizeDAG. 
Necessary for byval support on ARM.  Radar 7662569.

llvm-svn: 121412
 2010-12-09 21:25:20 +00:00
Jakob Stoklund Olesen
fe4b9ee934 Remember to filter out reserved rergisters from the allocation order. 
llvm-svn: 121411
 2010-12-09 21:20:46 +00:00
Jakob Stoklund Olesen
5bb5c67227 Add a forgotten initializer for CheckedFirstInterference. 
llvm-svn: 121410
 2010-12-09 21:20:44 +00:00
Owen Anderson
a8ac35b468 Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating 
the offset.  Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this.  It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.

llvm-svn: 121408
 2010-12-09 20:27:52 +00:00
Jim Grosbach
61fe7b9ee5 Rename CB/CBZ specific fixup accordingly. 
llvm-svn: 121404
 2010-12-09 19:50:12 +00:00