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9 Commits

Author SHA1 Message Date
Kevin Qin
a272df5db2 [AArch64] Fix a bug generating incorrect instruction when building small vector. 
This bug is introduced by r211144. The element of operand may be
smaller than the element of result, but previous commit can
only handle the contrary condition. This commit is to handle this
scenario and generate optimized codes like ZIP1.

llvm-svn: 213830
 2014-07-24 02:05:42 +00:00
Tim Northover
ca0f4dc4f0 AArch64/ARM64: move ARM64 into AArch64's place 
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

llvm-svn: 209577
 2014-05-24 12:50:23 +00:00
Tim Northover
d7f173214f AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64. 
I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.

The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.

Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.

llvm-svn: 209576
 2014-05-24 12:42:26 +00:00
Tim Northover
4ba95d4483 TableGen/ARM64: print aliases even if they have syntax variants. 
To get at least one use of the change (and some actual tests) in with its
commit, I've enabled the AArch64 & ARM64 NEON mov aliases.

llvm-svn: 208867
 2014-05-15 11:16:32 +00:00
Tim Northover
c327e9b2cf AArch64/ARM64: port more AArch64 tests to ARM64. 
llvm-svn: 206592
 2014-04-18 13:16:55 +00:00
Kevin Qin
9b14d101ea [AArch64 NEON] Add more scenarios to use perm instructions when lowering shuffle_vector 
This patch covered 2 more scenarios:

1.  Two operands of shuffle_vector are the same, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>

2. One of operands is undef, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>

After this patch, perm instructions will have chance to be emitted instead of lots of INS.

llvm-svn: 199069
 2014-01-13 01:56:29 +00:00
Kevin Qin
1370a1e1ee Refactored the implementation of AArch64 NEON instruction ZIP, UZP 
and TRN.
Fix a bug when mixed use of vget_high_u8() and vuzp_u8().

llvm-svn: 195716
 2013-11-26 03:26:47 +00:00
Kevin Qin
95c8b28223 [AArch64]Implement 128 bit register copy with NEON. 
llvm-svn: 195713
 2013-11-26 02:33:42 +00:00
Jiangning Liu
9c0eb8e7ba Implement AArch64 Neon instruction set Perm. 
llvm-svn: 194123
 2013-11-06 03:35:27 +00:00